Patents by Inventor Luis Vitorio Cargnini

Luis Vitorio Cargnini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250061063
    Abstract: A device may include memory media configured as cache media; and one or more circuits configured to perform operations including receiving memory access information, performing a mixture model analysis based on the memory access information to produce one or more scores, and updating the memory media based on the one or more scores. The memory media may include determining that at least one of the one or more scores is above a threshold and loading a portion of memory corresponding to the at least one of the one or more scores to the memory media. Updating the memory media may include determining that at least one of the one or more scores is below a threshold and removing a portion of memory corresponding to the at least one of the one or more scores from the memory media.
    Type: Application
    Filed: August 2, 2024
    Publication date: February 20, 2025
    Inventors: Luis Vitorio CARGNINI, Andrew Zhenwen CHANG, Yitu WANG, Mohammadreza SOLTANIYEH, Dongyang LI
  • Publication number: 20240419585
    Abstract: Systems and methods for demand-based storage are disclosed. A first storage device is coupled to a first computing device over a first link. The first storage device includes a storage medium and a processing circuit connected to the storage medium. The processing circuit may be configured to: receive a first request for a first storage capacity; transmit a second request for allocating at least a portion of the first storage capacity on a second storage device configured to communicate with the first storage device over a second link; receive a first storage command from the first computing device; generate a second storage command based on the first storage command; and transmit the second storage command to the second storage device for execution of the second storage command by the second storage device.
    Type: Application
    Filed: August 14, 2023
    Publication date: December 19, 2024
    Inventors: Ramdas Kachare, Hingkwan Huen, Luis Vitorio Cargnini, Hrishikesh Sathawane
  • Publication number: 20240397152
    Abstract: A device is disclosed. The device may include a storage device to store a content stream, and a network interface device to transmit a filtered content stream. A processing circuit may be connected to the storage device and the network interface device. The processing circuit may apply a filtering policy to the content stream to produce the filtered content stream.
    Type: Application
    Filed: August 25, 2023
    Publication date: November 28, 2024
    Inventors: Ramdas P. KACHARE, Dongwan ZHAO, Jimmy LAU, Luis Vitorio CARGNINI, Joseph FINDLEY
  • Publication number: 20240311318
    Abstract: A device is disclosed. An interface may connect the device to a processor. The interface may support a first protocol. A first storage and a second storage may the data. The second storage may support a second protocol different from the first protocol. A controller may be connected to the interface and the first storage. A bridge may be connected to the interface, the first storage, and the second storage. The bridge may include a filter configured to coordinate a data transfer between the first storage and the second storage.
    Type: Application
    Filed: November 17, 2023
    Publication date: September 19, 2024
    Inventors: Ramdas P. KACHARE, Jimmy LAU, Amir BEYGI, Mohammadreza SOLTANIYEH, Tinh LAC, Divya SUBBANNA, Mostafa AGHAEE, Dongwan ZHAO, William TIEN, Varadraj Ninad SINAI KAKODKAR, Luis Vitorio CARGNINI
  • Publication number: 20240311049
    Abstract: A memory device is disclosed. The memory device may include an interface to connect the memory device to a processor, a first storage for a data, and a second storage for the data. A controller may process a request received from the processor via the interface using the first storage or the second storage. A policy engine may instruct the controller regarding a storing of the data in the first storage or the second storage.
    Type: Application
    Filed: November 20, 2023
    Publication date: September 19, 2024
    Inventors: Ramdas P. KACHARE, Jimmy LAU, Mohammadreza SOLTANIYEH, Amir BEYGI, Tinh LAC, Divya SUBBANNA, Mostafa AGHAEE, Dongwan ZHAO, William TIEN, Varadraj Ninad SINAI KAKODKAR, Luis Vitorio CARGNINI
  • Patent number: 11705207
    Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: July 18, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Publication number: 20230195372
    Abstract: A device is disclosed. A storage device may include storage for a data and a controller to manage access to the storage. A network interface device may send the data across a network. A host interface may receive a request for the storage device or the network interface device.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 22, 2023
    Inventors: Ramdas KACHARE, Jingchi YANG, Hingkwan HUEN, Luis Vitorio CARGNINI
  • Publication number: 20230195320
    Abstract: A multi-function device is disclosed. The multi-function device may include a first connector for communicating with a storage device, a second connector for communicating with a first computational storage unit, a third connector for communicating with a second computational storage unit, and a fourth connector for communicating with a host processor. The multi-function device is configured to expose the storage device and the first computational storage unit to the host processor via the fourth connector.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 22, 2023
    Inventors: Ramdas KACHARE, Dongwan ZHAO, Jimmy LAU, Luis Vitorio CARGNINI, Joseph FINDLEY
  • Patent number: 11327808
    Abstract: A system and method for decentralized data processing includes receiving, by a first data processing unit of a data processing unit array, a user request and sending, by the first data processing unit, the user request to at least one of other data processing units of the data processing unit array. Each of the first data processing unit and the other data processing units include a dedicated non-volatile memory. The system and method also include receiving, by the first data processing unit, a code of execution results from each of the other data processing units that execute the user request, combining, by the first data processing unit, the code of execution results from the each of the other data processing units that execute the user request, and responding, by the first data processing unit, to the user request by transmitting the combined code of execution results.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 10, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitório Cargnini
  • Patent number: 11157692
    Abstract: In some implementations, a computing system is provided. The computing system includes a device. The device includes a non-volatile memory divided into a plurality of memory sub-arrays. Each memory sub-array comprises a plurality of selectable locations. A plurality of data processing units are communicatively coupled to the non-volatile memory in the absence of a central processing unit of the computing system. The data processing unit is assigned to process data of a memory sub-array, and configured to store the first data object in the non-volatile memory receive a first data object via a communication interface. The first data object comprises a first content and is associated with a first set of keywords. The data processing unit is also configured to add the first set of keywords to a local dictionary. The local dictionary is stored in the non-volatile memory. The data processing unit is further configured to determine whether the first data object is related to one or more other data objects.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Patent number: 11061728
    Abstract: A system and method for allocating memory to a heterogeneous address space includes identifying, by an operating system, at least one superset feature from an application configured to be executed on a host device. The address space associated with the application includes a plurality of supersets, and wherein the operating system allocates the memory to each of the plurality of supersets from a non-volatile memory or a volatile memory based upon the at least one superset feature.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: July 13, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Publication number: 20210082520
    Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Patent number: 10884664
    Abstract: A memory system includes a memory having a first executable memory cell and a compilation unit. The compilation unit is configured to receive a sequence of instructions from a host device, convert each of the sequence of instructions into an execution stream, load a first code from the execution stream into a code portion of the first executable memory cell and load a first data from the execution stream into a data portion of the first executable memory cell. The first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: January 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Patent number: 10884663
    Abstract: A computing unit includes a data processing unit having a plurality of executable memory cells. Each of the plurality of executable memory cells includes a code portion for storing code, a data portion for storing data, and an arithmetic and logic unit for applying the code to the data. The computing system also includes a compilation unit for converting a sequence of instructions into an execution stream. The execution stream includes the code and the data that is executed by the plurality of executable memory cells.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: January 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Patent number: 10885985
    Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Publication number: 20200311200
    Abstract: In some implementations, a computing system is provided. The computing system includes a device. The device includes a non-volatile memory divided into a plurality of memory sub-arrays. Each memory sub-array comprises a plurality of selectable locations. A plurality of data processing units are communicatively coupled to the non-volatile memory in the absence of a central processing unit of the computing system. The data processing unit is assigned to process data of a memory sub-array, and configured to store the first data object in the non-volatile memory receive a first data object via a communication interface. The first data object comprises a first content and is associated with a first set of keywords. The data processing unit is also configured to add the first set of keywords to a local dictionary. The local dictionary is stored in the non-volatile memory. The data processing unit is further configured to determine whether the first data object is related to one or more other data objects.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Publication number: 20200293222
    Abstract: A computing unit includes a data processing unit having a plurality of executable memory cells. Each of the plurality of executable memory cells includes a code portion for storing code, a data portion for storing data, and an arithmetic and logic unit for applying the code to the data. The computing system also includes a compilation unit for converting a sequence of instructions into an execution stream. The execution stream includes the code and the data that is executed by the plurality of executable memory cells.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Publication number: 20200293223
    Abstract: A memory system includes a memory having a first executable memory cell and a compilation unit. The compilation unit is configured to receive a sequence of instructions from a host device, convert each of the sequence of instructions into an execution stream, load a first code from the execution stream into a code portion of the first executable memory cell and load a first data from the execution stream into a data portion of the first executable memory cell. The first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Publication number: 20200257562
    Abstract: A system and method for allocating memory to a heterogeneous address space includes identifying, by an operating system, at least one superset feature from an application configured to be executed on a host device. The address space associated with the application includes a plurality of supersets, and wherein the operating system allocates the memory to each of the plurality of supersets from a non-volatile memory or a volatile memory based upon the at least one superset feature.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 13, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Publication number: 20200151020
    Abstract: A system and method for decentralized data processing includes receiving, by a first data processing unit of a data processing unit array, a user request and sending, by the first data processing unit, the user request to at least one of other data processing units of the data processing unit array. Each of the first data processing unit and the other data processing units include a dedicated non-volatile memory. The system and method also include receiving, by the first data processing unit, a code of execution results from each of the other data processing units that execute the user request, combining, by the first data processing unit, the code of execution results from the each of the other data processing units that execute the user request, and responding, by the first data processing unit, to the user request by transmitting the combined code of execution results.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 14, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Viacheslav Dubeyko, Luis Vitório Cargnini