Patents by Inventor Luis Vitorio Cargnini
Luis Vitorio Cargnini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250061063Abstract: A device may include memory media configured as cache media; and one or more circuits configured to perform operations including receiving memory access information, performing a mixture model analysis based on the memory access information to produce one or more scores, and updating the memory media based on the one or more scores. The memory media may include determining that at least one of the one or more scores is above a threshold and loading a portion of memory corresponding to the at least one of the one or more scores to the memory media. Updating the memory media may include determining that at least one of the one or more scores is below a threshold and removing a portion of memory corresponding to the at least one of the one or more scores from the memory media.Type: ApplicationFiled: August 2, 2024Publication date: February 20, 2025Inventors: Luis Vitorio CARGNINI, Andrew Zhenwen CHANG, Yitu WANG, Mohammadreza SOLTANIYEH, Dongyang LI
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Publication number: 20240419585Abstract: Systems and methods for demand-based storage are disclosed. A first storage device is coupled to a first computing device over a first link. The first storage device includes a storage medium and a processing circuit connected to the storage medium. The processing circuit may be configured to: receive a first request for a first storage capacity; transmit a second request for allocating at least a portion of the first storage capacity on a second storage device configured to communicate with the first storage device over a second link; receive a first storage command from the first computing device; generate a second storage command based on the first storage command; and transmit the second storage command to the second storage device for execution of the second storage command by the second storage device.Type: ApplicationFiled: August 14, 2023Publication date: December 19, 2024Inventors: Ramdas Kachare, Hingkwan Huen, Luis Vitorio Cargnini, Hrishikesh Sathawane
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Publication number: 20240397152Abstract: A device is disclosed. The device may include a storage device to store a content stream, and a network interface device to transmit a filtered content stream. A processing circuit may be connected to the storage device and the network interface device. The processing circuit may apply a filtering policy to the content stream to produce the filtered content stream.Type: ApplicationFiled: August 25, 2023Publication date: November 28, 2024Inventors: Ramdas P. KACHARE, Dongwan ZHAO, Jimmy LAU, Luis Vitorio CARGNINI, Joseph FINDLEY
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Publication number: 20240311318Abstract: A device is disclosed. An interface may connect the device to a processor. The interface may support a first protocol. A first storage and a second storage may the data. The second storage may support a second protocol different from the first protocol. A controller may be connected to the interface and the first storage. A bridge may be connected to the interface, the first storage, and the second storage. The bridge may include a filter configured to coordinate a data transfer between the first storage and the second storage.Type: ApplicationFiled: November 17, 2023Publication date: September 19, 2024Inventors: Ramdas P. KACHARE, Jimmy LAU, Amir BEYGI, Mohammadreza SOLTANIYEH, Tinh LAC, Divya SUBBANNA, Mostafa AGHAEE, Dongwan ZHAO, William TIEN, Varadraj Ninad SINAI KAKODKAR, Luis Vitorio CARGNINI
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Publication number: 20240311049Abstract: A memory device is disclosed. The memory device may include an interface to connect the memory device to a processor, a first storage for a data, and a second storage for the data. A controller may process a request received from the processor via the interface using the first storage or the second storage. A policy engine may instruct the controller regarding a storing of the data in the first storage or the second storage.Type: ApplicationFiled: November 20, 2023Publication date: September 19, 2024Inventors: Ramdas P. KACHARE, Jimmy LAU, Mohammadreza SOLTANIYEH, Amir BEYGI, Tinh LAC, Divya SUBBANNA, Mostafa AGHAEE, Dongwan ZHAO, William TIEN, Varadraj Ninad SINAI KAKODKAR, Luis Vitorio CARGNINI
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Patent number: 11705207Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.Type: GrantFiled: November 24, 2020Date of Patent: July 18, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
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Publication number: 20230195372Abstract: A device is disclosed. A storage device may include storage for a data and a controller to manage access to the storage. A network interface device may send the data across a network. A host interface may receive a request for the storage device or the network interface device.Type: ApplicationFiled: December 2, 2022Publication date: June 22, 2023Inventors: Ramdas KACHARE, Jingchi YANG, Hingkwan HUEN, Luis Vitorio CARGNINI
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Publication number: 20230195320Abstract: A multi-function device is disclosed. The multi-function device may include a first connector for communicating with a storage device, a second connector for communicating with a first computational storage unit, a third connector for communicating with a second computational storage unit, and a fourth connector for communicating with a host processor. The multi-function device is configured to expose the storage device and the first computational storage unit to the host processor via the fourth connector.Type: ApplicationFiled: February 10, 2023Publication date: June 22, 2023Inventors: Ramdas KACHARE, Dongwan ZHAO, Jimmy LAU, Luis Vitorio CARGNINI, Joseph FINDLEY
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Patent number: 11327808Abstract: A system and method for decentralized data processing includes receiving, by a first data processing unit of a data processing unit array, a user request and sending, by the first data processing unit, the user request to at least one of other data processing units of the data processing unit array. Each of the first data processing unit and the other data processing units include a dedicated non-volatile memory. The system and method also include receiving, by the first data processing unit, a code of execution results from each of the other data processing units that execute the user request, combining, by the first data processing unit, the code of execution results from the each of the other data processing units that execute the user request, and responding, by the first data processing unit, to the user request by transmitting the combined code of execution results.Type: GrantFiled: November 13, 2018Date of Patent: May 10, 2022Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitório Cargnini
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Patent number: 11157692Abstract: In some implementations, a computing system is provided. The computing system includes a device. The device includes a non-volatile memory divided into a plurality of memory sub-arrays. Each memory sub-array comprises a plurality of selectable locations. A plurality of data processing units are communicatively coupled to the non-volatile memory in the absence of a central processing unit of the computing system. The data processing unit is assigned to process data of a memory sub-array, and configured to store the first data object in the non-volatile memory receive a first data object via a communication interface. The first data object comprises a first content and is associated with a first set of keywords. The data processing unit is also configured to add the first set of keywords to a local dictionary. The local dictionary is stored in the non-volatile memory. The data processing unit is further configured to determine whether the first data object is related to one or more other data objects.Type: GrantFiled: March 29, 2019Date of Patent: October 26, 2021Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Patent number: 11061728Abstract: A system and method for allocating memory to a heterogeneous address space includes identifying, by an operating system, at least one superset feature from an application configured to be executed on a host device. The address space associated with the application includes a plurality of supersets, and wherein the operating system allocates the memory to each of the plurality of supersets from a non-volatile memory or a volatile memory based upon the at least one superset feature.Type: GrantFiled: February 12, 2019Date of Patent: July 13, 2021Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Publication number: 20210082520Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.Type: ApplicationFiled: November 24, 2020Publication date: March 18, 2021Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
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Patent number: 10884664Abstract: A memory system includes a memory having a first executable memory cell and a compilation unit. The compilation unit is configured to receive a sequence of instructions from a host device, convert each of the sequence of instructions into an execution stream, load a first code from the execution stream into a code portion of the first executable memory cell and load a first data from the execution stream into a data portion of the first executable memory cell. The first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.Type: GrantFiled: March 14, 2019Date of Patent: January 5, 2021Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Patent number: 10884663Abstract: A computing unit includes a data processing unit having a plurality of executable memory cells. Each of the plurality of executable memory cells includes a code portion for storing code, a data portion for storing data, and an arithmetic and logic unit for applying the code to the data. The computing system also includes a compilation unit for converting a sequence of instructions into an execution stream. The execution stream includes the code and the data that is executed by the plurality of executable memory cells.Type: GrantFiled: March 14, 2019Date of Patent: January 5, 2021Assignee: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Patent number: 10885985Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.Type: GrantFiled: December 30, 2016Date of Patent: January 5, 2021Assignee: Western Digital Technologies, Inc.Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
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Publication number: 20200311200Abstract: In some implementations, a computing system is provided. The computing system includes a device. The device includes a non-volatile memory divided into a plurality of memory sub-arrays. Each memory sub-array comprises a plurality of selectable locations. A plurality of data processing units are communicatively coupled to the non-volatile memory in the absence of a central processing unit of the computing system. The data processing unit is assigned to process data of a memory sub-array, and configured to store the first data object in the non-volatile memory receive a first data object via a communication interface. The first data object comprises a first content and is associated with a first set of keywords. The data processing unit is also configured to add the first set of keywords to a local dictionary. The local dictionary is stored in the non-volatile memory. The data processing unit is further configured to determine whether the first data object is related to one or more other data objects.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Publication number: 20200293222Abstract: A computing unit includes a data processing unit having a plurality of executable memory cells. Each of the plurality of executable memory cells includes a code portion for storing code, a data portion for storing data, and an arithmetic and logic unit for applying the code to the data. The computing system also includes a compilation unit for converting a sequence of instructions into an execution stream. The execution stream includes the code and the data that is executed by the plurality of executable memory cells.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Publication number: 20200293223Abstract: A memory system includes a memory having a first executable memory cell and a compilation unit. The compilation unit is configured to receive a sequence of instructions from a host device, convert each of the sequence of instructions into an execution stream, load a first code from the execution stream into a code portion of the first executable memory cell and load a first data from the execution stream into a data portion of the first executable memory cell. The first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Publication number: 20200257562Abstract: A system and method for allocating memory to a heterogeneous address space includes identifying, by an operating system, at least one superset feature from an application configured to be executed on a host device. The address space associated with the application includes a plurality of supersets, and wherein the operating system allocates the memory to each of the plurality of supersets from a non-volatile memory or a volatile memory based upon the at least one superset feature.Type: ApplicationFiled: February 12, 2019Publication date: August 13, 2020Applicant: Western Digital Technologies, Inc.Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
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Publication number: 20200151020Abstract: A system and method for decentralized data processing includes receiving, by a first data processing unit of a data processing unit array, a user request and sending, by the first data processing unit, the user request to at least one of other data processing units of the data processing unit array. Each of the first data processing unit and the other data processing units include a dedicated non-volatile memory. The system and method also include receiving, by the first data processing unit, a code of execution results from each of the other data processing units that execute the user request, combining, by the first data processing unit, the code of execution results from the each of the other data processing units that execute the user request, and responding, by the first data processing unit, to the user request by transmitting the combined code of execution results.Type: ApplicationFiled: November 13, 2018Publication date: May 14, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Viacheslav Dubeyko, Luis Vitório Cargnini