Abstract: A circuit and method for reducing power consumption in an I/R receiver system includes determining a duty cycle of a command cycle comprising a series of command pulses separated by nulls and enabling and disabling selective active components of an I/R receiver system in accordance with the duty cycle. In an embodiment, the enabling of the active components commences during a null prior to the arrival of a new command pulse. In a further example embodiment, the enabling includes first enabling a first set of active components having a first settling time, waiting for at least the first settling time, and then second enabling a second set of active components having a second settling time.

Abstract: A receiver having an intermediate frequency error correction circuit includes a mixer having a source input, a local oscillator input, and an IF output, an adjustable frequency local oscillator having an output coupled to the local oscillator input of the mixer, an IF filter having an input coupled to the IF output of the mixer and an IF filtered output, where the IF filter has an IF filter frequency response, and control circuitry coupled to the local oscillator such that the frequency of the local oscillator can be varied to at least: partially correct an IF frequency error.

Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.

Abstract: In an embodiment, set forth by way of example and not limitation, a receiver with automatic gain includes a receiver stage, an AGC stage, and a digital processor which collectively define an AGC loop. Preferably, the AGC stage has a control circuit and a feedback circuit with matched transfer characteristics. A digital processor is operative to develop a gain control signal to set a desired gain level of the receiver stage to an optimal level based upon a waveform analysis derived from the gain feedback signal.

Abstract: An example bandpass filter calibration system includes a MUX, first and second signal sources coupled to inputs of the MUX, a bandpass filter coupled to an output of the MUX, a rectification circuit including a plurality of rectifiers having a corresponding plurality of rectifier outputs coupled to an output of the bandpass filter, a summer having a plurality of inputs coupled to the plurality of rectifier outputs, a low pass filter coupled to an output of the summer, an ADC coupled to an output of the low pass filter, and a calibration processor unit coupled to an output of the ADC. The calibration processor unit controls the MUX to selectively apply the first signal source and the second signal source to the bandpass filter and calibrates the bandpass filter by a least one of increasing filter center frequency and decreasing filter center frequency of the bandpass filter.

Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.

Abstract: In an embodiment, set forth by way of example and not limitation, a receiver with automatic gain includes a receiver stage, an AGC stage, and a digital processor which collectively define an AGC loop. Preferably, the AGC stage has a control circuit and a feedback circuit with matched transfer characteristics. A digital processor is operative to develop a gain control signal to set a desired gain level of the receiver stage to an optimal level based upon a waveform analysis derived from the gain feedback signal.

Abstract: An example bandpass filter calibration system includes a MUX, first and second signal sources coupled to inputs of the MUX, a bandpass filter coupled to an output of the MUX, a rectification circuit including a plurality of rectifiers having a corresponding plurality of rectifier outputs coupled to an output of the bandpass filter, a summer having a plurality of inputs coupled to the plurality of rectifier outputs, a low pass filter coupled to an output of the summer, an ADC coupled to an output of the low pass filter, and a calibration processor unit coupled to an output of the ADC. The calibration processor unit controls the MUX to selectively apply the first signal source and the second signal source to the bandpass filter and calibrates the bandpass filter by a least one of increasing filter center frequency and decreasing filter center frequency of the bandpass filter.