Patents by Inventor Luiz DeRose

Luiz DeRose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10761820
    Abstract: A parallelization assistant tool system to assist in parallelization of a computer program is disclosed. The system directs the execution of instrumented code of the computer program to collect performance statistics information relating to execution of loops within the computer program. The system provides a user interface for presenting to a programmer the performance statistics information collected for a loop within the computer program so that the programmer can prioritize efforts to parallelize the computer program. The system generates inlined source code of a loop by aggressively inlining functions substantially without regard to compilation performance, execution performance, or both. The system analyzes the inlined source code to determine the data-sharing attributes of the variables of the loop. The system may generate compiler directives to specify the data-sharing attributes of the variables.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 1, 2020
    Assignee: Cray, Inc.
    Inventors: Heidi Poxon, John Levesque, Luiz DeRose, Brian H. Johnson
  • Patent number: 10698813
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Publication number: 20190163637
    Abstract: A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer (“ORB”). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.
    Type: Application
    Filed: March 6, 2018
    Publication date: May 30, 2019
    Inventors: Sanyam Mehta, James Robert Kohn, Daniel Jonathan Ernst, Heidi Lynn Poxon, Luiz DeRose
  • Patent number: 10303610
    Abstract: A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer (“ORB”). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 28, 2019
    Assignee: Cray, Inc.
    Inventors: Sanyam Mehta, James Robert Kohn, Daniel Jonathan Ernst, Heidi Lynn Poxon, Luiz DeRose
  • Publication number: 20190042435
    Abstract: A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer (“ORB”). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.
    Type: Application
    Filed: March 6, 2018
    Publication date: February 7, 2019
    Inventors: Sanyam Mehta, James Robert Kohn, Daniel Jonathan Ernst, Heidi Lynn Poxon, Luiz DeRose
  • Patent number: 10185659
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 22, 2019
    Assignee: Cray, Inc.
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Publication number: 20180322064
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Application
    Filed: July 12, 2018
    Publication date: November 8, 2018
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Publication number: 20180165209
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Patent number: 9946654
    Abstract: A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer (“ORB”). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: April 17, 2018
    Assignee: Cray Inc.
    Inventors: Sanyam Mehta, James Robert Kohn, Daniel Jonathan Ernst, Heidi Lynn Poxon, Luiz DeRose
  • Publication number: 20180074963
    Abstract: A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer (“ORB”). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.
    Type: Application
    Filed: October 26, 2016
    Publication date: March 15, 2018
    Inventors: Sanyam Mehta, James Robert Kohn, Daniel Jonathan Ernst, Heidi Lynn Poxon, Luiz DeRose
  • Publication number: 20170206068
    Abstract: An optimization system to apply directives to a computer program without having to perform repeated front-end compilations of source code of the computer program is provided. In some embodiments, the optimization system performs a first compilation of the source code of the program to generate first front-end code and first back-end code of the computer program. The compilation includes a first front-end compilation and a first back-end compilation. The optimization system identifies a compiler directive to apply to a location within the first front-end code. The optimization system then performs a second back-end compilation of the first front-end code factoring in the compiler directive to generate second back-end code affected by the compiler directive.
    Type: Application
    Filed: May 9, 2016
    Publication date: July 20, 2017
    Inventors: Brian H. Johnson, Heidi Poxon, Luiz DeRose, Gary W. Elsesser, Clayton D. Andreasen, John Levesque
  • Publication number: 20160110174
    Abstract: A parallelization assistant tool system to assist in parallelization of a computer program is disclosed. The system directs the execution of instrumented code of the computer program to collect performance statistics information relating to execution of loops within the computer program. The system provides a user interface for presenting to a programmer the performance statistics information collected for a loop within the computer program so that the programmer can prioritize efforts to parallelize the computer program. The system generates inlined source code of a loop by aggressively inlining functions substantially without regard to compilation performance, execution performance, or both. The system analyzes the inlined source code to determine the data-sharing attributes of the variables of the loop. The system may generate compiler directives to specify the data-sharing attributes of the variables.
    Type: Application
    Filed: December 22, 2015
    Publication date: April 21, 2016
    Inventors: Heidi Poxon, John Levesque, Luiz DeRose, Brian H. Johnson
  • Patent number: 9250877
    Abstract: A parallelization assistant tool system to assist in parallelization of a computer program is disclosed. The system directs the execution of instrumented code of the computer program to collect performance statistics information relating to execution of loops within the computer program. The system provides a user interface for presenting to a programmer the performance statistics information collected for a loop within the computer program so that the programmer can prioritize efforts to parallelize the computer program. The system generates inlined source code of a loop by aggressively inlining functions substantially without regard to compilation performance, execution performance, or both. The system analyzes the inlined source code to determine the data-sharing attributes of the variables of the loop. The system may generate compiler directives to specify the data-sharing attributes of the variables.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: February 2, 2016
    Assignee: Cray Inc.
    Inventors: Heidi Poxon, John Levesque, Luiz DeRose, Brian H. Johnson
  • Publication number: 20150089468
    Abstract: A parallelization assistant tool system to assist in parallelization of a computer program is disclosed. The system directs the execution of instrumented code of the computer program to collect performance statistics information relating to execution of loops within the computer program. The system provides a user interface for presenting to a programmer the performance statistics information collected for a loop within the computer program so that the programmer can prioritize efforts to parallelize the computer program. The system generates inlined source code of a loop by aggressively inlining functions substantially without regard to compilation performance, execution performance, or both. The system analyzes the inlined source code to determine the data-sharing attributes of the variables of the loop. The system may generate compiler directives to specify the data-sharing attributes of the variables.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: Cray Inc.
    Inventors: Heidi Poxon, John Levesque, Luiz DeRose, Brian H. Johnson
  • Publication number: 20120311537
    Abstract: Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions of the node. A second set of statistics may be displayed in the interior of the node. A third set of statistics may be displayed in response to selecting the node.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 6, 2012
    Applicant: Cray Inc.
    Inventors: Luiz DeRose, Dean T. Johnson
  • Patent number: 8286135
    Abstract: Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions of the node. A second set of statistics may be displayed in the interior of the node. A third set of statistics may be displayed in response to selecting the node.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: October 9, 2012
    Assignee: Cray Inc.
    Inventors: Luiz DeRose, Dean T. Johnson
  • Publication number: 20080092121
    Abstract: Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions of the node. A second set of statistics may be displayed in the interior of the node. A third set of statistics may be displayed in response to selecting the node.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 17, 2008
    Inventors: Luiz DeRose, Dean Johnson
  • Patent number: 7308681
    Abstract: A method and apparatus for creating a compressed trace for a program, wherein events are compressed separately to provide improved compression and tracing. A sequence of events for a program is selected, and a sequence of values is then determined for each of the selected events occurring during an execution of the program. Each sequence of values is then compressed to generate a compressed sequence of values for each event. These values are then ordered in accordance with information stored in selected events (such as for example, branch events), where the ordered values correspond to the trace.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: December 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kattamuri Ekanadham, Pratap Pattnaik, Simone Sbaraglia, Luiz A. DeRose
  • Publication number: 20050091643
    Abstract: A method and apparatus for creating a compressed trace for a program, wherein events are compressed separately to provide improved compression and tracing. A sequence of events for a program is selected, and a sequence of values is then determined for each of the selected events occurring during an execution of the program. Each sequence of values is then compressed to generate a compressed sequence of values for each event. These values are then ordered in accordance with information stored in selected events (such as for example, branch events), where the ordered values correspond to the trace.
    Type: Application
    Filed: October 28, 2003
    Publication date: April 28, 2005
    Applicant: International Business Machines Corporation
    Inventors: Kattamuri Ekanadham, Pratap Pattnaik, Simone Sbaraglia, Luiz DeRose