Abstract: Technologies for strain engineering in gate-all-around (GAA) field-effect transistors (FETs) are disclosed. In an illustrative embodiment, the source/drain contacts for N-type metal-oxide-semiconductor (NMOS) FETs extend deeper into the source/drain regions than the source/drain contacts for P-type metal-oxide-semiconductor (PMOS) FETs. The source/drain contacts for the NMOS FETs may cause a tensile strain in the channel of the NMOS FETs, while the source/drain region of the PMOS FETS may cause a compressive strain in the channel of the PMOS FETs. The tensile and compressive strains on the NMOS and PMOS channels, respectively, can increase the speed of the NMOS and PMOS transistors.

Abstract: A method for monitoring precursor material in a carrier stream of a fabrication system comprises depositing a film of precursor material on a surface of a QCM sensor and determining a starting resonance frequency of the QCM sensor with the deposited film of precursor material. The resonance frequency of the QCM sensor is measured during operation of the fabrication system and compared with the starting resonance frequency. A system error is issued when the measured resonance frequency differs from the corresponding starting resonance frequency by more than a threshold value. A system correction is automatically implemented and configured to restore the QCM sensor to the starting resonance frequency.

Abstract: Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.

Abstract: Integrated circuit (IC) devices having shared, dual-metal gates for complementary transistors. An IC device includes a shared gate structure over first and second stacks of nanoribbons with complementary conductivities and a substrate, and the gate structure includes first, second, and third gate metals with the first gate metal over and around the nanoribbons in the first stack, the second gate metal over and around the nanoribbons in the second stack, and the third gate metal around and between the nanoribbons in the first stack, between the first and second stacks, in contact with both the first and second gate metals, and extending beyond the first metal over the substrate. The first gate metal may act as a temple for selective deposition of the third gate metal. The second gate metal may be conformally deposited over the nanoribbons in the second stack and on the third gate metal.

Abstract: Contact over active gate (COAG) structures with gate recess for gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using a gate recess for accommodating gate insulating cap layers, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. An epitaxial source or drain structure is coupled to the vertical stack of horizontal nanowires or the fin. A gate stack is over the vertical stack of horizontal nanowires or the fin, the gate stack including a gate dielectric and a gate electrode, the gate electrode including a gate electrode material layer, a lower fill material, and an upper fill material, the upper fill material distinct from the lower fill material. A gate insulating cap structure is on the upper fill material of the gate stack.

Abstract: Integrated circuit structures having dual stress gates are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires, and a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires. An NMOS gate electrode is over the first vertical stack of horizontal nanowires, the NMOS gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires. A PMOS gate electrode is over the second vertical stack of horizontal nanowires, the PMOS gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires. The tensile layer of the NMOS gate electrode is not included in the PMOS gate electrode.

Abstract: A method for monitoring precursor material in a carrier stream of a fabrication system comprises depositing a film of precursor material on a surface of a QCM sensor and determining a starting resonance frequency of the QCM sensor with the deposited film of precursor material. The resonance frequency of the QCM sensor is measured during operation of the fabrication system and compared with the starting resonance frequency. A system error is issued when the measured resonance frequency differs from the corresponding starting resonance frequency by more than a threshold value. A system correction is automatically implemented and configured to restore the QCM sensor to the starting resonance frequency.

Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.

Abstract: A system and method for determining the changes in resonance frequency in crystal microbalance (CM) sensors and the resulting changes in the determination of incremental mass on the CM sensors caused by temperature. Dual mode resonances and coefficients are used in a deconvolution process to determine and extract the frequency shift caused by temperature to provide the temperature compensated incremental mass (?M). In one embodiment, dual mode analysis is provided using a mass mode (e.g., the c-mode fundamental frequency (fc100)) and a temperature mode (e.g., the anharmonic frequency (fc102)) and associated coefficients. In other embodiments that are more sensitive to temperature changes, dual mode analysis is provided using the b-mode fundamental frequency (fb100) as the temperature-mode and associated coefficients.

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.