Abstract: Managing feedthrough wiring for an integrated circuit via design data is provided. The integrated circuit includes a sub-unit, which further includes a feedthrough wire that forwards a digital signal from an input of the sub-unit to an output of the sub-unit. The design data describes the feedthrough wiring of the sub-unit. Management of the feedthrough wiring includes determining physical constraint data from parameter data of the feedthrough wire and timing constraint data related to the feedthrough wire from the physical constraint data. The design data is then synthesized based on the timing constraint data.

Abstract: A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Abstract: Managing feedthrough wiring for an integrated circuit via design data is provided. The integrated circuit includes a sub-unit, which further includes a feedthrough wire that forwards a digital signal from an input of the sub-unit to an output of the sub-unit. The design data describes the feedthrough wiring of the sub-unit. Management of the feedthrough wiring includes determining physical constraint data from parameter data of the feedthrough wire and timing constraint data related to the feedthrough wire from the physical constraint data. The design data is then synthesized based on the timing constraint data.

Abstract: There is provided a computer implemented method for processing a formal specification of a digital circuit. The specification comprises information about a signal path for forwarding a digital signal from a source to a sink. The method comprises inputting the formal specification; identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification; inputting physical design constraints; and calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.

Abstract: A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Abstract: There is provided a computer implemented method for processing a formal specification of a digital circuit. The specification comprises information about a signal path for forwarding a digital signal from a source to a sink. The method comprises inputting the formal specification; identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification; inputting physical design constraints; and calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.