Abstract: A computer implemented method for a multi-layer integrated circuit routing tool connecting sources with nets to sinks in a hierarchical multi-layer integrated circuit design environment, the method including creating a cycle reach table containing a first set of information parameters for two dimensional nets per metal layer combination, creating a repeater reach table containing a second set of information parameters per constraint class, preparing a working list of nets, preparing a list of blocks larger than repeater reach dimensions, connecting a source pin to a sink pin on preassigned metal layers, by routing the net based on the given constraint class.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: Systems and methods to perform integrated circuit development include identifying one or more multi-sink nets in a design of the integrated circuit. Each of the one or more multi-sink nets includes a source that supplies signals to two or more sinks. A method includes determining a wire tag for each of the two or more sinks of each of the one or more multi-sink nets. Each wire tag defines characteristics of a wire connecting the source to the sink, and the characteristics include a wire width and a range of metal layers within the integrated circuit for traversal of the wire. The method also includes providing the design and the wire tags for fabrication of the integrated circuit.

Abstract: Systems and methods to perform integrated circuit development include identifying one or more multi-sink nets in a design of the integrated circuit. Each of the one or more multi-sink nets includes a source that supplies signals to two or more sinks. A method includes determining a wire tag for each of the two or more sinks of each of the one or more multi-sink nets. Each wire tag defines characteristics of a wire connecting the source to the sink, and the characteristics include a wire width and a range of metal layers within the integrated circuit for traversal of the wire. The method also includes providing the design and the wire tags for fabrication of the integrated circuit.

Abstract: Methods are provided for optimizing a routing of a signal path in terms of delay and signal integrity in a semiconductor device. The signal path includes at least one track in a metal layer. The method includes selecting an already routed original signal path to be optimized, modifying at least one original routing parameter, creating an alternative signal path based on the modified routing parameter value, determining at least one timing value describing the delay and signal integrity of the alternative signal path and signal integrity, and replacing the already routed original signal path by the alternative signal path based on the timing value indicating that the alternative signal path complies with predefined constraints related to the delay and signal integrity.

Abstract: A method is provided for facilitating an integrated circuit design layout. The method includes receiving a netlist including a plurality of subnets. For each subnet, the method also includes obtaining a Steiner net length value and related net delays in a signal path for a metal wiring layer using timings of all involved circuits of the subnet, and determining whether the net delay is smaller than a predefined value. On a negative outcome of the determination, a wire delay is ascertained for the named metal wiring layer based on a maximum buffer distance retrieved from a cycle reach table, and determining whether the ascertained wire delay is below the related net delay. On a positive outcome of the second determination, a next increased metal wire width is selected and a metal wire based wire delay for the named metal wiring layer including a buffer is ascertained.

Abstract: Methods are provided for optimizing a routing of a signal path in terms of delay and signal integrity in a semiconductor device. The signal path includes at least one track in a metal layer. The method includes selecting an already routed original signal path to be optimized, modifying at least one original routing parameter, creating an alternative signal path based on the modified routing parameter value, determining at least one timing value describing the delay and signal integrity of the alternative signal path and signal integrity, and replacing the already routed original signal path by the alternative signal path based on the timing value indicating that the alternative signal path complies with predefined constraints related to the delay and signal integrity.

Abstract: A method is provided for facilitating an integrated circuit design layout. The method includes receiving a netlist including a plurality of subnets. For each subnet, the method also includes obtaining a Steiner net length value and related net delays in a signal path for a metal wiring layer using timings of all involved circuits of the subnet, and determining whether the net delay is smaller than a predefined value. On a negative outcome of the determination, a wire delay is ascertained for the named metal wiring layer based on a maximum buffer distance retrieved from a cycle reach table, and determining whether the ascertained wire delay is below the related net delay. On a positive outcome of the second determination, a next increased metal wire width is selected and a metal wire based wire delay for the named metal wiring layer including a buffer is ascertained.

Abstract: A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first timing details and the second timing details.

Abstract: A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first timing details and the second timing details.

Abstract: A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first and the second timing details.

Abstract: A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first and the second timing details.

Abstract: Optimized buffer placement is provided based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. An estimated slack is calculated for each branch, the branches are arranged according to the calculated slack, decoupling buffers are inserted in all branches except the most critical branch(es), the most critical branch(es) are globally routed and slew conditions are fixed within this branch, and at least one next branch is globally routed and slew conditions are fixed therein.

Abstract: Optimized buffer placement is provided based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. An estimated slack is calculated for each branch, the branches are arranged according to the calculated slack, decoupling buffers are inserted in all branches except the most critical branch(es), the most critical branch(es) are globally routed and slew conditions are fixed within this branch, and at least one next branch is globally routed and slew conditions are fixed therein.

Abstract: A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. The method includes: calculating an estimated slack for each branch based on cycle reach, calculating a minimum slack for each branch, arranging branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the most critical branch(es) and placing decoupling buffers close to the source, globally routing the most critical branch(es) and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this branch(es), and routing all remaining branches.

Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

Abstract: A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. The method includes: calculating an estimated slack for each branch based on cycle reach, calculating a minimum slack for each branch, arranging branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the most critical branch(es) and placing decoupling buffers close to the source, globally routing the most critical branch(es) and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this branch(es), and routing all remaining branches.