Abstract: Architecture in which a data bus is by its data outputs is interconnected with N parallel submodules (9 or 19) specialized to compute CRC values from given parts of data bus word (9.1 or 19.1), the number of which (N) is given by the maximal number of data packets transferred in a single data bus word; a unique form of intermediate CRC values distribution between submodules (9) through signals (9.2, 9.4) and register (10) in serial version of top-level architecture or between submodules (19) through signals (19.2, 19.4, 19.5, 19.6) and register (20) in parallel version of the top-level architecture, where the internal structure of individual submodules (9 or 19) is specifically tailored for such an arrangement; and a structure of each submodule (9 or 19) capable of processing one part of data bus word separates the main CRC value computation is disclosed.