Abstract: A network includes a first plurality of nodes operating in a first clock domain based on a first clock source, a second plurality of nodes operating in a second clock domain based on a second clock source, and synchronization circuitry accessible to both of the clock domains without requiring network traffic between the clock domains. The synchronization circuitry is configured to periodically calculate a drift rate between the time of day in the respective clock domains. Each node in one of the clock domains is configured to, when sending a message to a node in the other of the clock domains, calculate a time of day in the other of the clock domains based on an actual time of day in the one of the clock domains and the drift rate, and to include, in the message to the node in the other clock domain, the calculated time of day.

Abstract: A network includes a first plurality of nodes operating in a first clock domain based on a first clock source, a second plurality of nodes operating in a second clock domain based on a second clock source, and synchronization circuitry accessible to both of the clock domains without requiring network traffic between the clock domains. The synchronization circuitry is configured to periodically calculate a drift rate between the time of day in the respective clock domains. Each node in one of the clock domains is configured to, when sending a message to a node in the other of the clock domains, calculate a time of day in the other of the clock domains based on an actual time of day in the one of the clock domains and the drift rate, and to include, in the message to the node in the other clock domain, the calculated time of day.

Abstract: A network includes a first plurality of nodes operating in a first clock domain based on a first clock source, a second plurality of nodes operating in a second clock domain based on a second clock source, and synchronization circuitry accessible to both of the clock domains without requiring network traffic between the clock domains. The synchronization circuitry is configured to periodically calculate a drift rate between the time of day in the respective clock domains. Each node in one of the clock domains is configured to, when sending a message to a node in the other of the clock domains, calculate a time of day in the other of the clock domains based on an actual time of day in the one of the clock domains and the drift rate, and to include, in the message to the node in the other clock domain, the calculated time of day.

Abstract: A media content converter, for converting media content into network packets, includes logic circuitry, a header generator and a multiplexer. The logic circuitry is configured to partition the media content into payloads for the network packets. The header generator configured to generate packet headers for the network packets, by populating with data a plurality of header fields according to a predefined header format. The multiplexer is configured to stream a sequence of the network packets for transmission over a communication network, by combining the generated packet headers from the header generator with the corresponding payloads from the logic circuitry.

Abstract: A packet generator includes a checksum calculator configured to distinguish, in a communication packet belonging to a sequence of packets, between (i) one or more constant values of a header of the packet, the one or more constant values remaining unchanged across the packets in the sequence, (ii) a payload of the packet, and (iii) one or more variable values of the header, the one or more variable values changing among the packets in the sequence, to determine a constant-values partial checksum calculated over the constant values of the header, to calculate a payload partial checksum over the payload, to calculate a final checksum value for the packet based on (i) the constant-values partial checksum, (ii) the payload partial checksum and (iii) the variable values of the header, and to insert the final checksum value into the packet. An egress interface transmits the packet over a network.

Abstract: A conversion pipeline includes a media input stage, a packetizer, a MAC engine and a PHY interface. The media input stage is configured to receive from a media source a sequence of media frames carrying media content. The packetizer is configured to convert the media frames into a sequence of Ethernet packets by generating headers and appending portions of media frames to corresponding generated headers, including appending a first portion of a first media frame to a first generated header before the first media frame is fully received. The MAC engine is configured to commence outputting a first Ethernet packet as an uninterrupted unit, the first Ethernet packet including the first header and payload bits corresponding to the first portion of the first media frame, before the first media frame is fully received. The PHY interface is configured to transmit the Ethernet packets over a network.

Abstract: A media content converter, for converting media content into network packets, includes logic circuitry, a header generator and a multiplexer. The logic circuitry is configured to partition the media content into payloads for the network packets. The header generator configured to generate packet headers for the network packets, by populating with data a plurality of header fields according to a predefined header format. The multiplexer is configured to stream a sequence of the network packets for transmission over a communication network, by combining the generated packet headers from the header generator with the corresponding payloads from the logic circuitry.

Abstract: A conversion pipeline includes a media input stage, a packetizer, a MAC engine and a PHY interface. The media input stage is configured to receive from a media source a sequence of media frames carrying media content. The packetizer is configured to convert the media frames into a sequence of Ethernet packets by generating headers and appending portions of media frames to corresponding generated headers, including appending a first portion of a first media frame to a first generated header before the first media frame is fully received. The MAC engine is configured to commence outputting a first Ethernet packet as an uninterrupted unit, the first Ethernet packet including the first header and payload bits corresponding to the first portion of the first media frame, before the first media frame is fully received. The PHY interface is configured to transmit the Ethernet packets over a network.

Abstract: A packet generator includes a checksum calculator configured to distinguish, in a communication packet belonging to a sequence of packets, between (i) one or more constant values of a header of the packet, the one or more constant values remaining unchanged across the packets in the sequence, (ii) a payload of the packet, and (iii) one or more variable values of the header, the one or more variable values changing among the packets in the sequence, to determine a constant-values partial checksum calculated over the constant values of the header, to calculate a payload partial checksum over the payload, to calculate a final checksum value for the packet based on (i) the constant-values partial checksum, (ii) the payload partial checksum and (iii) the variable values of the header, and to insert the final checksum value into the packet. An egress interface transmits the packet over a network.

Abstract: Systems, methods, and other embodiments associated with ordering packets into a transmission order within a queue are described. According to one embodiment, an apparatus includes shaper logic configured to (i) respectively determine launch times for packets received from a host bus, and (ii) order the packets into a transmission order according to the launch times. The launch times are expected transmission times for the packets that are provided according to one or more attributes associated with each respective one of the packets. The apparatus includes a queue configured to store the packets in the transmission order for transmission onto a network in a single stream. The shaper logic is configured to merge the packets from multiple streams into the transmission order when providing the packets to the queue.

Abstract: A system is provided for configuring a configurable device. The system includes an internal bus in communication with registers and to a configuration circuit. The configuration circuit may include its own registers. The configuration circuit tests a content of at least one of the registers and performs an operation in accordance with the result of the test.

Abstract: A system is provided for configuring a configurable device. The system includes an internal bus in communication with registers and to a configuration circuit. The configuration circuit may include its own registers. The configuration circuit tests a content of at least one of the registers and performs an operation in accordance with the result of the test.