Patents by Inventor Lukas Valek

Lukas Valek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260139405
    Abstract: Silicon carbide substrates are in demand for high power applications such as electric vehicles, solar panels, and industrial electronics. A physical vapor transport (PVT) reactor for growth of silicon carbide ingots can be improved by attaching a cooling assembly to a top end of a PVT growth crucible. By varying the number, size, and spacing of cooling elements within the cooling assembly, radial temperature variation inside the PVT growth crucible can be adjusted, independent of axial temperature variation. More uniform radial temperature profiles result in lower stress, fewer crystal defects, and improved silicon carbide wafer quality.
    Type: Application
    Filed: November 18, 2024
    Publication date: May 21, 2026
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Lukas VALEK, Jan HYBL, Rastislav MACKO
  • Publication number: 20260049412
    Abstract: A growth system is disclosed. The growth system may include a crucible at least partially enclosed by an insulation layer, a growth region located within the crucible and configured to hold a silicon carbide (SiC) seed crystal, a source-material region located within the crucible and configured to hold an SiC source material. The growth system may further include a barrier located within the crucible and configured to separate the source-material region and the growth region. In addition, the growth system may include a heating element located around the crucible and configured together with an opening in the insulation layer to provide a temperature gradient with a decreasing temperature in a direction from the source material toward the growth region. The growth system may also include a vent extending through the barrier from the source-material region to the growth region.
    Type: Application
    Filed: August 15, 2024
    Publication date: February 19, 2026
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Rastislav MACKO, Lukas VALEK, Jan HYBL
  • Publication number: 20240150926
    Abstract: A crucible for manufacturing semiconductor crystals may be disposed adjacent to a heating element. The crucible may include a first seed crystal site and a second seed crystal site at opposed ends of the crucible. A compartment may be defined between an outer wall and an inner wall of the crucible, where the inner wall is formed with a porous graphite membrane. Source powder loaded into the compartment may then be heated by the heating element to sublimate and diffuse from the compartment and through the inner wall to provide crystal growth of a first seed crystal at the first seed crystal site and of a second seed crystal at the second seed crystal site.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Radek JESKO, Lukas VALEK, Jan TESIK
  • Patent number: 8846500
    Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered gettering structure that can be used to control wafer warpage.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: David Lysacek, Jana Vojtechovska, Lubomir Dornak, Petr Kostelnik, Lukas Valek, Petr Panek
  • Publication number: 20120146024
    Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered Bettering structure that can be used to control wafer warpage.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Inventors: David Lysacek, Jana Vojtechovska, Lubomir Dornak, Petr Kostelnik, Lukas Valek, Petr Panek
  • Patent number: 7737004
    Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: June 15, 2010
    Assignee: Semiconductor Components Industries LLC
    Inventors: David Lysacek, Michal Lorenc, Lukas Valek
  • Publication number: 20080003782
    Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.
    Type: Application
    Filed: July 3, 2006
    Publication date: January 3, 2008
    Inventors: David Lysacek, Michal Lorenc, Lukas Valek