Abstract: A display substrate and a display device. The display substrate includes a driving circuit layer, a first scanning line and a second scanning line. The driving circuit layer includes pixel units arranged in an array form, each pixel unit includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit, the pixel driving circuit includes a first transistor and a second transistor, an active pattern of the first transistor includes a first channel region, an active pattern of the second transistor includes a second channel region, the first channel region is located on a side of the first scanning line away from the second scanning line, and the second channel region is located on a side of the second scanning line away from the first scanning line.

Abstract: A display substrate and driving method thereof, a display device are provided. The display substrate includes: a base substrate, and a plurality of repeating units and a plurality of data lines on the base substrate, the plurality of repeating units are divided into plurality of repeating unit columns; each repeating unit includes a plurality of subpixels, the subpixel includes a subpixel driving circuit, the subpixel driving circuit includes a data writing transistor, a writing control transistor and a driving transistor; the first electrode of the data writing transistor is coupled to the corresponding data line, the second electrode of the data writing transistor is coupled to the first electrode of the writing control transistor, and the second electrode of the writing control transistor is coupled to the gate of the driving transistor.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate, data lines and sub-pixels on the base substrate. The sub-pixels include a sub-pixel driving circuit and a light-emitting element including a first electrode. The sub-pixel driving circuit includes a driving transistor and a data writing transistor having a first electrode coupled to the data line through a second connection structure. A second electrode of the driving transistor is coupled to the first electrode through a first connection structure. The first and second connection structures are in a non-aperture region of the sub-pixel. Orthographic projections of the first and second connection structures onto the base substrate are arranged along a first direction. An orthographic projection of the second connection structure onto the base substrate and an aperture region of the sub-pixel are along a second direction which intersects the first direction.

Abstract: A display substrate including a base substrate and a driving module arranged on the base substrate, the driving module includes at least one driving unit, and the driving unit includes N stages of driving circuits; N is a positive integer, n is a positive integer less than or equal to N; the nth stage of driving circuit includes a (2n?1)th stage of output circuit, a 2nth stage of output circuit and a first node control circuit; the first node is electrically connected to the (2n?1)th stage of output circuit and the 2nth stage of output circuit respectively through a first connection line; the driving module also includes a scanning line; there are at least two mutually independent overlapping portions between the orthographic projection of the first connection line on the base substrate and the orthographic projection of the scanning line on the base substrate.

Abstract: Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.

Abstract: A display substrate, including: a plurality of partition control signal lines disposed on a base substrate; and a plurality of sub-pixels disposed on the base substrate, at least one of the sub-pixels includes a pixel circuit and a light emitting device. The pixel circuit includes a switch transistor, a first partition control transistor, a drive transistor and a first initialization transistor. The first partition control transistor is electrically connected to the switch transistor, the first initialization transistor, the drive transistor and at least one partition control signal line. The first partition control transistor is configured to: in response to a partition control signal on the partition control signal line, selectively transmit a received first initialization signal to a gate electrode of the drive transistor in an initialization phase, and selectively transmit a received data signal to the gate electrode of the drive transistor in a data writing phase.

Abstract: A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.

Abstract: Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a base substrate including a display area and a first frame area located on one side of the display area; and a first power bus at least located in the first frame area. The first power bus includes a first sub-bus, a second sub-bus and at least two connecting wires. The first sub-bus is located between the second sub-bus and the display area, and the first sub-bus is electrically connected to the second sub-bus by means of the at least two connecting wires.

Abstract: A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.

Abstract: The disclosure provides a display substrate, which has a display region and a peripheral region, and includes a base substrate, a plurality of sub-pixels, a first power signal line and a second power signal line at least partially located in the display region, a first power signal bus and a second power signal bus located in the peripheral region; the sub-pixels are located in the display region; the first power signal line and the second power signal line are electrically connected to the first power signal bus and the second power signal bus, respectively; the second power signal bus includes a first part disposed on a side of the first power signal bus close to the display region, and a second part disposed on a side of the first power signal bus away from the display region, so as to at least partially surround the first power signal bus.

Abstract: A display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a base substrate, and a display area and a mounting area provided on the base substrate; the display area includes multiple second pixel circuits, the mounting area includes multiple first pixel circuits, and an area of an orthographic projection of a first pixel circuit on the base substrate is smaller than an area of an orthographic projection of a second pixel circuit on the base substrate.

Abstract: Provided are a manufacturing method of a display substrate, a display substrate, and a display device. The display substrate includes: a base substrate; and a top-gate type thin film transistor located on a side of the base substrate, the top-gate type thin film transistor comprises an active layer, a gate insulation layer and a gate electrode sequentially disposed in a direction away from the base substrate. A side surface of the gate insulation layer close to the gate electrode extends beyond an edge of the gate electrode in a direction parallel to the base substrate, and a side surface of the active layer close to the gate insulation layer extends beyond an edge of the gate insulation layer in the direction parallel to the base substrate.

Abstract: Provided is drive backplane. The drive backplane includes: a substrate, including a plurality of light transmitting regions and a plurality of sub-pixel regions; a pixel drive circuit and an anode block that are disposed in the sub-pixel region, the pixel drive circuit being electrically connected to the anode block; and repair lines and repair electrodes that are disposed in the light transmitting regions, an end of the repair line being spaced from the repair electrode; wherein, an end, departing from the repair electrode, of the repair line is electrically connected to the anode block in a first sub-pixel region, the repair electrode is electrically connected to the anode block in a second sub-pixel region.

Abstract: A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 ?m and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.

Abstract: A display substrate, including: a plurality of partition control signal lines disposed on a base substrate; and a plurality of sub-pixels disposed on the base substrate, at least one of the sub-pixels includes a pixel circuit and a light emitting device. The pixel circuit includes a switch transistor, a first partition control transistor, a drive transistor and a first initialization transistor. The first partition control transistor is electrically connected to the switch transistor, the first initialization transistor, the drive transistor and at least one partition control signal line. The first partition control transistor is configured to: in response to a partition control signal on the partition control signal line, selectively transmit a received first initialization signal to a gate electrode of the drive transistor in an initialization phase, and selectively transmit a received data signal to the gate electrode of the drive transistor in a data writing phase.

Abstract: The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.

Abstract: A display substrate including a base substrate and a plurality of pixel units on the base substrate. Each pixel unit includes: a plurality of sub-pixels and at least one scanning line. The plurality of sub-pixels are arranged sequentially in a first direction, each sub-pixels includes a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit is coupled to the light-emitting element. Each scanning line includes a first scanning conductive layer and a second scanning conductive layer arranged in a laminated manner, the first scanning conductive layer is coupled to the second scanning conductive layer, the first scanning conductive layer includes at least a portion extending in the first direction, and the first scanning conductive layer is coupled to a plurality of sub-pixel driving circuits in the plurality of sub-pixels.

Abstract: A display substrate, a method for fabricating the same, and a display panel are provided. The display substrate includes: a substrate, and a first conductive layer, at least two insulation layers, and a second conductive layer, the second conductive layer being electrically connected with the first conductive layer through via-holes, and the at least two insulation layers including a first insulation layer in contact with the first conductive layer, wherein the display substrate further includes an assisting alignment structure on the surface of the first insulation layer, and the orthographic projection of the assisting alignment structure surrounds at least part of the edge of the orthographic projection of the first via-hole in the first insulation layer on the substrate, so that the orthographic projection of the first via-hole on the first conductive layer lies within the pattern of the first conductive layer.

Abstract: A display substrate and a display device are provided. The display substrate includes a light emitting element disposed on a base substrate, and an encapsulation layer, a connection layer, a light extraction layer, a polarization conversion layer and a polarization layer stacked sequentially at a light exiting side of the light emitting element. The light extraction layer is configured to convert at least a portion of light emitted by the light emitting element incident onto the light extraction layer into circularly polarized light with a set rotational direction to pass through the light extraction layer. The polarization conversion layer is configured to convert the circularly polarized light passing through the light extraction layer into linearly polarized light, with a polarization direction parallel to a direction of a light transmission axis of the polarization layer; the connection layer is configured to bond the light extraction layer to the encapsulation layer.