Patents by Inventor Luke Garner

Luke Garner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11705389
    Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Luke Garner, Liwei Cheng, Lauren Link, Cheng Xu, Ying Wang, Bin Zou, Chong Zhang
  • Publication number: 20200395282
    Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Andrew J. BROWN, Luke GARNER, Liwei CHENG, Lauren LINK, Cheng XU, Ying WANG, Bin ZOU, Chong ZHANG
  • Publication number: 20090085187
    Abstract: Methods and associated apparatus of reducing stress in a package Those methods may comprise providing a package comprising a die coupled to a substrate, wherein the substrate is disposed on an LGA socket, and wherein a TIM is disposed on a top surface of the die, and then attaching a thermal solution to the TIM, wherein at least one standoff is attached between the thermal solution and the substrate.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventors: Ward Scott, Luke Garner, Ioan Sauciuc