Abstract: According to one embodiment, a network is disclosed. The network includes a server computer and a client computer. The client computer accesses an authentication stack during power on self test (POST) that enables authentication of boot code that is to be downloaded from the server computer prior to control being passed to the operating system.

Abstract: A method for providing security to a computer system is described. Specifically, the computer periodically polls for a Bluetooth electronic device or other similar wireless electronic device. If the computer locates such a Bluetooth electronic device, the computer requests authentication from the Bluetooth electronic device. The user of the electronic device is given access to the computer system only if the computer recognizes the identification of the Bluetooth electronic device and is able to validate the authentication information provided by the Bluetooth electronic device through an encrypted channel.

Abstract: A user-authentication sub-system and approach for user authentication. The user authentication sub-system of one aspect includes at least a first input mechanism to receive first multi-factor authentication data associated with Z authentication factors, a cryptographic engine to encrypt the first multi-factor authentication data, and a separated user authentication, non-volatile data store to store the encrypted first multi-factor authentication data. The sub-system further includes a processing unit to determine whether second authentication data received via the at least first input mechanism matches a subset of the first multi-factor authentication data, the second authentication data associated with N authentication factors where N is less than or equal to Z.

Abstract: A method and apparatus for authenticating a user's identity are disclosed. In one embodiment, a data collector continuously receives and collects a stream of biometric data from a user. After the data collector passes on the biometric data to a data matcher, the data matcher continuously processes the data to authenticate the user's identity.

Abstract: An approach for providing services to an open platform implementing Subscriber Identity Module (SIM) capabilities without the need for a discrete, physical SIM device. For one aspect, a protected communications channel is established with a computing system, the computing system providing SIM Authentication, Authorization and Accounting (AAA) capabilities without the use of a discrete hardware SIM device. SIM secret data is provisioned to the computing system over the protected communications channel.

Abstract: An approach for providing Subscriber Identity Module (SIM) capabilities in an open platform without the need for a discrete, physical SIM device. For one aspect, a computing system provides for secure provisioning of SIM data and algorithms, for example, protected storage of SIM secret data objects, and protected execution of SIM algorithms that provide for Authentication, Authorization and Accounting (AAA) capabilities currently associated with discrete hardware SIM devices.

Abstract: In one embodiment, the invention provides a method comprising storing user authentication information in a hardware structure of a computer system, the hardware structure including a security mechanism to protect the stored authentication information from unauthorized access, and authenticating a user of the computer system by comparing user input authentication information with the stored authentication information.

Abstract: A hardware implementation for quotient prediction overrule in high speed higher radix SRT division computation circuits. A quotient prediction PLA receives a data segment of the divisor, together with data values from one or more multiplexors. One multiplexor receives as input a partial remainder from a carry-propagate-adder (CPA), which CPA combines into nonredundant form redundant sum and carry vectors derived from a carry-save-adder (CSA) which determines the next partial remainder. The PLA evaluates the next most significant bits (MSBs) of the divisor together with the next MSBs of the next (unlatched) partial remainder to determine the next quotient bits. The quotient estimates given by the quotient prediction PLA are then transmitted to both quotient and remainder generation logic, including a divisior multiple gating multiplexor. The quotient estimate signals together with a sign signal determine the divisor multiple to be used in the next division iteration during the next clock cycle.

Abstract: A hardware floating point remainder generator is disclosed for performing a remainder (REM) function by receiving two floating point numbers (X and Y), by generating the remainder of X/Y according to a series of radix 4 SRT non-restoring division cycles and at most one single bit restoring division step, and by delivering the remainder.

Abstract: A hardware logic arrangement for subtraction using a 3:2 carry-save-adder (CSA) for use with high speed floating point computation circuits. Three operands to be combined are routed to the three inputs of the CSA via separate multiplexors (MUXs) and appropriate inverting logic. Output sum and carry vectors are routed via further MUXs to separate latch storage registers. Subtraction executed as addition of the inverse of an operand is implemented by routing a constant "1" to the MUX steering the output carry vector to its associated latch.

Abstract: A hardware logic arrangement for quotient correction in high speed higher radix non-restoring division computation circuits producing alternative quotient results of the form Q and Q-1. A two bit per clock quotient bit stream is taken as the output from an divider and selectively latched into positive and negative weighted quotients. These redundant vectors are then seperately steered via appropriate steering logic to a carry-propogate-adder (CPA). An exclusive-OR (XOR) logic block is inserted between the steering logic for one of the vectors and the subtrahend input of the CPA. Operation of the XOR block is governed by a first control signal. A second control signal is coupled to the carry-in input of the CPA. After the last iteration of the division sequence, either Q or Q-1 alternative forms of the result quotient may be produced in the clock cycle required by selectively invoking 2's complement addition when combining the redundant weighted quotients.