Patents by Inventor Luke Graham
Luke Graham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250109559Abstract: Zero-ascend omnispecies (ZAO) attraction system includes a fish passage attraction module that can be deployed in a fishway where water flows downstream. The fish passage attraction module includes a body having a first end and an opposite second end, first adaptor adjacent the first end and second adaptor adjacent the second end. The adaptors are configured to alter water flow fields downstream of the module so as to attract fish to an entrance thereof.Type: ApplicationFiled: November 18, 2024Publication date: April 3, 2025Applicant: LITTORAL POWER SYSTEMS, INC.Inventors: David J. Duquette, Katherine Leighton, Luke Graham, Vincent Bryan
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Patent number: 12188194Abstract: Zero-ascend omnispecies (ZAO) attraction system includes a fish passage attraction module that can be deployed in a fishway where water flows downstream. The fish passage attraction module includes a body having a first end and an opposite second end, first adaptor adjacent the first end and second adaptor adjacent the second end. The adaptors are configured to alter water flow fields downstream of the module so as to attract fish to an entrance thereof.Type: GrantFiled: July 8, 2022Date of Patent: January 7, 2025Assignee: LITTORAL POWER SYSTEMS, INC.Inventors: David J. Duquette, Katherine Leighton, Luke Graham, Vincent Bryan
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Publication number: 20230011618Abstract: Zero-ascend omnispecies (ZAO) attraction system includes a fish passage attraction module that can be deployed in a fishway where water flows downstream. The fish passage attraction module includes a body having a first end and an opposite second end, first adaptor adjacent the first end and second adaptor adjacent the second end. The adaptors are configured to alter water flow fields downstream of the module so as to attract fish to an entrance thereof.Type: ApplicationFiled: July 8, 2022Publication date: January 12, 2023Inventors: David J. Duquette, Katherine Leighton, Luke Graham, Vince Bryan
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Patent number: 10693277Abstract: A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.Type: GrantFiled: August 6, 2019Date of Patent: June 23, 2020Assignee: II-VI Delaware Inc.Inventors: Luke A. Graham, Sonia Quadery, Deepa Gazula, Haiquan Yang
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Patent number: 10644482Abstract: An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.Type: GrantFiled: March 12, 2019Date of Patent: May 5, 2020Assignee: Finisar CorporationInventors: Luke Graham, Andy MacInnes
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Publication number: 20190393678Abstract: A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.Type: ApplicationFiled: August 6, 2019Publication date: December 26, 2019Inventors: Luke A. Graham, Sonia Quadery, Deepa Gazula, Haiquan Yang
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Patent number: 10374391Abstract: A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.Type: GrantFiled: September 28, 2017Date of Patent: August 6, 2019Assignee: FINISAR CORPORATIONInventors: Luke A. Graham, Sonia Quadery, Deepa Gazula, Haiquan Yang
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Publication number: 20190207369Abstract: An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.Type: ApplicationFiled: March 12, 2019Publication date: July 4, 2019Inventors: Luke Graham, Andy MacInnes
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Patent number: 10230215Abstract: An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.Type: GrantFiled: August 8, 2017Date of Patent: March 12, 2019Assignee: FINISAR CORPORATIONInventors: Luke Graham, Andy MacInnes
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Publication number: 20180090909Abstract: A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.Type: ApplicationFiled: September 28, 2017Publication date: March 29, 2018Inventors: Luke A. Graham, Sonia Quadery, Deepa Gazula, Haiquan Yang
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Publication number: 20180041009Abstract: An etched planarized VCSEL includes: an active region; a blocking region over the active region, and defining apertures therein; and conductive channel cores in the apertures, wherein the conductive channel cores and blocking region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the blocking region over the active region; etching the apertures in the blocking region; and forming the conductive channel cores in the apertures of the blocking region. Another etched planarized VCSEL includes: an active region; a conductive region over the active region, and defining apertures therein; and blocking cores in the apertures, wherein the blocking cores and conductive region form an isolation region. A method of making the VCSEL includes: forming the active region; forming the conductive region over the active region; etching the apertures in the conductive region; and forming the blocking cores in the apertures of the conductive region.Type: ApplicationFiled: August 8, 2017Publication date: February 8, 2018Inventors: Luke Graham, Andy MacInnes
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Patent number: 9318872Abstract: A VCSEL can include a graphene intra-cavity absorber having at least one graphene region and at least one dielectric region adjacent to the graphene region. The VCSEL can also include a graphene electrode electronically coupled with at least one graphene region. The VCSEL can also include a contact region adjacent with at least one dielectric region. The VCSEL can also include a contact electrode electronically coupled with the contact region. The VCSEL can also include a base electrode electronically coupled with a base of a semiconductor region of the VCSEL. The graphene intra-cavity absorber can include at least two graphene regions sandwiching at least one dielectric region therebetween.Type: GrantFiled: January 5, 2015Date of Patent: April 19, 2016Assignee: FINISAR CORPORATIONInventors: Luke A. Graham, Ralph H. Johnson, James K. Guenter
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Publication number: 20150194789Abstract: A VCSEL can include a graphene intra-cavity absorber having at least one graphene region and at least one dielectric region adjacent to the graphene region. The VCSEL can also include a graphene electrode electronically coupled with at least one graphene region. The VCSEL can also include a contact region adjacent with at least one dielectric region. The VCSEL can also include a contact electrode electronically coupled with the contact region. The VCSEL can also include a base electrode electronically coupled with a base of a semiconductor region of the VCSEL. The graphene intra-cavity absorber can include at least two graphene regions sandwiching at least one dielectric region therebetween.Type: ApplicationFiled: January 5, 2015Publication date: July 9, 2015Inventors: Luke A. Graham, Ralph H. Johnson, James K. Guenter
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Patent number: 8442365Abstract: An optical subassembly for low-feedback coupling of light from a light source into an optical waveguide such as an optical fiber is described. The optical subassembly has an aspherical lens with surface sag having a rotationally symmetrical sag component without having a cone sag component, and a rotationally asymmetrical helical component for reducing coupling of light reflected from the optical fiber tip back into the laser aperture by causing a significant portion of the reflected light to encircle the laser aperture. The lens shape and the height of the helix are selected so that tight focusing onto the fiber tip is preserved, while the optical feedback is reduced.Type: GrantFiled: December 29, 2009Date of Patent: May 14, 2013Assignee: JDS Uniphase CorporationInventor: Luke Graham
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Publication number: 20120236891Abstract: A VCSEL can include: one or more quantum wells having (Al)InGaAs; two or more quantum well barriers having Al(In)GaAs bounding the one or more quantum well layers; and one or more transitional monolayers deposited between each quantum well layer and quantum well barrier, wherein the quantum wells, barriers and transitional monolayers are substantially devoid of traps. The one or more transitional monolayers include GaP, GaAs, and/or GaAsP. Alternatively, the VCSEL can include two or more transitional monolayers of AlInGaAs with a barrier-side monolayer having lower In and higher Al compared to a quantum well side monolayer that has higher In and lower Al.Type: ApplicationFiled: March 19, 2012Publication date: September 20, 2012Applicant: FINISAR CORPORATIONInventors: Ralph H. Johnson, Jimmy Alan Tatum, Andrew N. MacInnes, Jerome K. Wade, Luke A. Graham
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Publication number: 20100329605Abstract: An optical subassembly for low-feedback coupling of light from a light source into an optical waveguide such as an optical fiber is described. The optical subassembly has an aspherical lens with surface sag having a rotationally symmetrical sag component without having a cone sag component, and a rotationally asymmetrical helical component for reducing coupling of light reflected from the optical fiber tip back into the laser aperture by causing a significant portion of the reflected light to encircle the laser aperture. The lens shape and the height of the helix are selected so that tight focusing onto the fiber tip is preserved, while the optical feedback is reduced.Type: ApplicationFiled: December 29, 2009Publication date: December 30, 2010Inventor: Luke GRAHAM
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Patent number: 7802930Abstract: A device comprising: an optical subassembly has a lens rear surface including one or more facets for scattering at least some of the light transmitted through the lens rear surface.Type: GrantFiled: March 4, 2008Date of Patent: September 28, 2010Assignee: JDS Uniphase CorporationInventors: Jack L. Jewell, Luke A. Graham
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Patent number: 7796850Abstract: Optical systems comprise one or more optical pathways including lenses that are offset with respect to each other and lenses that are offset with respect to optical fibers.Type: GrantFiled: June 11, 2008Date of Patent: September 14, 2010Assignee: JDS Uniphase CorporationInventors: Jack L. Jewell, Luke A. Graham
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Publication number: 20090310915Abstract: Optical systems comprise one or more optical pathways including lenses that are offset with respect to each other and lenses that are offset with respect to optical fibers.Type: ApplicationFiled: June 11, 2008Publication date: December 17, 2009Applicant: JDS Uniphase CorporationInventors: Jack L. Jewell, Luke A. Graham
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Publication number: 20090252192Abstract: A device including a laser with reduced feedback.Type: ApplicationFiled: April 8, 2008Publication date: October 8, 2009Applicant: JDS Uniphase CorporationInventors: Jack L. Jewell, Luke A. Graham