Patents by Inventor Luke J. Garner

Luke J. Garner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11676873
    Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Dinesh Padmanabhan Ramalekshmi Thanu, Hemanth K. Dhavaleswarapu, Venkata Suresh Guthikonda, John J. Beatty, Yonghao An, Marco Aurelio Cartas Ayala, Luke J. Garner, Peng Li
  • Publication number: 20200185290
    Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.
    Type: Application
    Filed: June 30, 2017
    Publication date: June 11, 2020
    Inventors: Dinesh PADMANABHAN RAMALEKSHMI THANU, Hemanth K. DHAVALESWARAPU, Venkata Suresh GUTHIKONDA, John J. BEATTY, Yonghao AN, Marco Aurelio CARTAS AYALA, Luke J. GARNER, Peng LI
  • Publication number: 20190043778
    Abstract: Embodiments are generally directed to a swaging process for complex integrated heat spreaders. An embodiment of an integrated heat spreader includes components, each of the components including one or more swage points; and a multiple swage joints, each swage joint including a swage pin joining two or more components, wherein components are joined into a single integrated heat spreader unit by the swage joints.
    Type: Application
    Filed: December 26, 2015
    Publication date: February 7, 2019
    Inventors: Zhizhong TANG, Shinobu KOURAKATA, Kazuo OGATA, Paul R. START, Syadwad JIAN, William Nicholas LABANOK, Wei HU, Peng LI, Douglas R. YOUNG, Gregory S. CONSTABLE, John J. Beatty, Pardeep K. BHATTI, Luke J. GARNER, Aravindha R. ANTONISWAMY
  • Publication number: 20190006259
    Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate and a second die disposed adjacent the first die on the substrate. A cooling solution is attached to the substrate, wherein a rib extends from a central region of the cooling solution and is attached to the substrate. The rib is disposed between the first die and the second die.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Dinesh Padmanabhan Ramalekshmi Thanu, Wei Hu, James C. Matayabas, JR., Baris Bicen, Luke J. Garner, Hemanth Dhavaleswarapu