Abstract: Technical solutions are described for executing a computer instruction including an asynchronous operation. An example method includes computing parameters associated with the asynchronous operation, and transmitting a command for executing the asynchronous operation by an external device. The method also includes intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers. The method also includes receiving a response to the asynchronous operation. In response to the asynchronous operation being a success, executing a next instruction by the processing element. In response to the asynchronous operation being a failure, a processing element accesses the parameters from the log registers, and restarts the asynchronous operation using the parameters from the one or more log registers.

Abstract: Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.

Abstract: Embodiments are directed to a method of optimizing power consumption in an electrical device. The method includes receiving, by a processor, instructions to enter a wait state, and identifying, by the processor, a parameter associated with the instructions to enter a wait state. The method continues with initiating, by the processor, instructions to enter a low-power mode based on the parameter, initiating, by the processor, instructions to exit a low-power mode based on the parameter, and providing, via a user interface, a user with notice of a current state of the processor. The parameter includes runtime information, instructional information, and scheduled operations.

Abstract: Technical solutions are described for executing a computer instruction including an asynchronous operation. An example method includes computing parameters associated with the asynchronous operation, and transmitting a command for executing the asynchronous operation by an external device. The method also includes intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers. The method also includes receiving a response to the asynchronous operation. In response to the asynchronous operation being a success, executing a next instruction by the processing element. In response to the asynchronous operation being a failure, a processing element accesses the parameters from the log registers, and restarts the asynchronous operation using the parameters from the one or more log registers.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: Technical solutions are described for executing a computer instruction including an asynchronous operation. An example method includes computing parameters associated with the asynchronous operation, and transmitting a command for executing the asynchronous operation by an external device. The method also includes intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers. The method also includes receiving a response to the asynchronous operation. In response to the asynchronous operation being a success, executing a next instruction by the processing element. In response to the asynchronous operation being a failure, a processing element accesses the parameters from the log registers, and restarts the asynchronous operation using the parameters from the one or more log registers.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Abstract: Embodiments are directed to a method of optimizing power consumption in an electrical device. The method includes receiving, by a processor, instructions to enter a wait state, and identifying, by the processor, a parameter associated with the instructions to enter a wait state. The method continues with initiating, by the processor, instructions to enter a low-power mode based on the parameter, initiating, by the processor, instructions to exit a low-power mode based on the parameter, and providing, via a user interface, a user with notice of a current state of the processor. The parameter includes runtime information, instructional information, and scheduled operations.

Abstract: Technical solutions are described for executing a computer instruction including an asynchronous operation. An example method includes computing parameters associated with the asynchronous operation, and transmitting a command for executing the asynchronous operation by an external device. The method also includes intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers. The method also includes receiving a response to the asynchronous operation. In response to the asynchronous operation being a success, executing a next instruction by the processing element. In response to the asynchronous operation being a failure, a processing element accesses the parameters from the log registers, and restarts the asynchronous operation using the parameters from the one or more log registers.

Abstract: Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.

Abstract: Technical solutions are described for profiling an execution of a computer program. An example method includes setting a program-counter indicator to a first state in response to updating a program counter register. The method further includes profiling the execution of the computer program by periodically sampling the program counter register according to a sampling time-interval. Sampling the program counter register includes recording a content of the program counter register in response to the program-counter indicator being in the first state. The method also includes increasing the sampling time-interval.

Abstract: An exemplary embodiment of the present invention is a method and system for isolating dropped packets in a computer network. A request for network analysis that includes a source node and a destination node is received by the invention. A map of the expected path between the two points, including the probes along the route is then generated. A capture filter profile for each probe along the route is created. A request to perform data collection is transmitted, along with the capture filter profile, to each of the probes along the route. Data is received back from the data collection in the form of a data log. Exception data is generated by comparing the data log to the expected path between the two points. Additional embodiments include a system and storage medium for isolating dropped packets in a computer network.

Abstract: An exemplary embodiment of the present invention is a method and system for isolating dropped packets in a computer network. A request for network analysis that includes a source node and a destination node is received by the invention. A map of the expected path between the two points, including the probes along the route is then generated. A capture filter profile for each probe along the route is created. A request to perform data collection is transmitted, along with the capture filter profile, to each of the probes along the route. Data is received back from the data collection in the form of a data log. Exception data is generated by comparing the data log to the expected path between the two points. Additional embodiments include a system and storage medium for isolating dropped packets in a computer network.