Abstract: A computer system has physical pages of memory subject to access by input/output (“I/O”) devices, and a certain table with entries associating the physical pages with the I/O devices. Responsive to a request for data be moved from a first physical page to a second physical page, an entry is selected for the first physical page in the table. The selected entry indicates an association of the first physical page and one of the I/O devices. Arbitration is temporarily disabled for the selected I/O device so that I/O operations for the I/O device are temporarily disabled. Once arbitration is disabled for the device the data is moved from the first physical page to a second one of the physical pages and the entry is updated in the table to reflect a new association between the I/O device and the second physical page.

Abstract: A method and system for controlling the allocation of a data processing system's resources among two or more components competing for the resources. An internal system value is modified to yield a modified system value. A utilization history is created by mapping a component's utilization of the system resources. Then, the priority of the component is calculated utilizing the utilization history and the modified system value within a priority calculation.

Abstract: Apparatus and methods for dispatching fixed priority threads using a global run queue in a multiple run queue system. The apparatus includes a controller, memory, initial load balancing device, idle load balancing device, periodic load balancing device, and starvation load balancing device. The apparatus performs initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.

Abstract: Apparatus and methods for dispatching fixed priority threads using a global run queue in a multiple run queue system. The apparatus includes a controller, memory, initial load balancing device, idle load balancing device, periodic load balancing device, and starvation load balancing device. The apparatus performs initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.

Abstract: An apparatus, method and computer program product for minimizing the negative effects that occur when simple locks are highly contended among processors which may or may not have identical latencies to the memory that represents a given lock, are provided. The apparatus, method and computer program product minimize these effects by converting simple locks such that they act as standard simple locks when there is no contention and act as krlocks when there is contention for a lock. In this way, the number of processors spinning on a lock is limited to a single processor, thereby reducing the number of processors that are in a wait state and not performing any useful work.

Abstract: A method and system are disclosed for handling exceptions generated by a particular processor among a number of processors within a multiprocessor data processing system. The data processing system includes a global queue from which threads are dispatched in a priority order for execution by the processors and a number of local dispatch flags, which are each associated with one of the processors. In response to an occurrence of an exception during execution of a particular thread by a particular processor, a state of the particular thread, which is at least partially defined by volatile data within the particular processor, is saved. A selected exception handler associated with the exception is then executed. Next, a determination is made whether resumption of the particular thread depends upon an occurrence of a specified event.

Abstract: Each processor in a multiprocessor system has a local clock. Variables "TIME.sub.-- DELTA" and "TIME.sub.-- PREV", are defined for each processor and maintained in databases. TIME.sub.-- DELTA is decremented or incremented to zero, dependent upon whether a positive or negative time delta is specified by the user, and is modified at each clock tick. TIME.sub.-- PREV represents the time to bring the current processor up to the remaining processors' time. A user-specified time adjustment causes an ADJTIME system call. When a second ADJTIME call is subsequently made responsive to a next adjustment, the system examines each processor's TIME.sub.-- DELTA and determines which processor has advanced the furthest and calculates the time for each processor to catch up with this most-advanced processor. This time value is thereafter stored in the TIME.sub.-- PREV field and applied at the next system clock tick. Finally, the ADJTIME call updates each processor's TIME.sub.

Abstract: A computer-implemented method, computer system, and memory for performing a fork operation of a parent process is provided. The parent process includes one or more threads, each having a kernel stack. The method includes the steps of locating the kernel stacks in a first memory location (e.g., segment 1) if the parent process is multi-threaded, in response to an initiation of a fork by a calling thread, switching the kernel stack of the calling thread to a second memory location if the parent process is multi-threaded, and copying the second memory location (e.g., segment 2) to create a child process.

Abstract: A method and system for using a single lock data structure for executing either development or non-development lock primitives contained within a kernel. The kernel includes a mode indication flag, which can be set by the user, for indicating whether the kernel is to operate in a development or a non-development mode. During the execution of the kernel, the mode indication flag is examined and the appropriate set of lock primitives is overlayed. During execution of the kernel in development mode, the single lock data structure is received in the kernel, and a development lock data structure is allocated. The data from the single lock data structure is copied to the development lock data structure, and the lock data structure is overloaded (redefined) as a pointer to the physical address of the development lock data structure. Finally, the lock data structure is initialized to point to the physical address of the development lock data structure.