Patents by Inventor Luke P. Hood

Luke P. Hood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7769938
    Abstract: In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: August 3, 2010
    Assignee: Intel Corporation
    Inventors: Shivnandan D. Kaushik, Keshavan K. Tiruvallur, James B. Crossland, Sridhar Muthrasanallur, Rajesh S. Parthasarathy, Luke P. Hood
  • Patent number: 7627706
    Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: December 1, 2009
    Assignee: Intel Corporation
    Inventors: Shivnandan D. Kaushik, Keshavan K. Tiruvallur, James B. Crossland, Sridhar Muthrasanallur, Rajesh S. Parthasarathy, Luke P. Hood
  • Publication number: 20090070511
    Abstract: In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 12, 2009
    Inventors: Shivnandan D. Kaushik, Keshavan K. Tiruvallur, James B. Crossland, Sridhar Muthrasanallur, Rajesh S. Parthasarathy, Luke P. Hood
  • Publication number: 20090070551
    Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 12, 2009
    Inventors: Shivnandan D. Kaushik, Keshavan K. Tiruvallur, James B. Grossland, Sridhar Muthrasanallur, Rajesh S. Parthasarathy, Luke P. Hood