Abstract: The present invention discloses a Ginkgo Biloba extract composite formulation and the use thereof, comprising: a Ginkgo Biloba extract, a Salvia miltiorrhiza extract, astaxanthin, Astragalus, Coenzyme Q10 and American Ginseng; the Ginkgo Biloba extract comprises Ginkgo flavonoids and Ginkgolides; the Salvia miltiorrhiza extract comprises tanshinone II A, Danshensu and Salvianolic acid. The invention combines the Ginkgo Biloba extract, the Salvia miltiorrhiza extract, astaxanthin, Astragalus, Coenzyme Q10 and American Ginseng for comprehensive preparation; effectively conditions the disordered body through comprehensive nourishing and conditioning, thus truly solving the “fatigue” and supplementing vitality, and recuperating the body to a healthy state.

Abstract: Embodiments employ the blockchain to democratize the creation of debt and credit in a digital environment. The embodiments are directed to systems and methods for executing debt and credit transactions in the digital environment. The systems and methods register a first user and second user with a credit protocol application, including providing a respective first and second user identifier recorded in the blockchain. The systems and methods establish a relationship, via the credit protocol application, between a first computing device of the first user and a second computing device of the second user by validating: (i) the first identifier includes an address of the first computing device, and (ii) the second identifier includes an address of the second computing device. Based on the established relationship, the systems and methods send from the first computing device a request for the transaction. The systems and methods, by the second user at the second computing device, receive and confirm the request.

Abstract: A Stevia rebaudiana plant is characterized by Rebaudioside A (RA) content of 6-20% dry weight and total steviol glycosides content of 15-28% dry weight in the leaf. The plant is developed using selective breeding technologies and identified by RAPD gene analysis.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

Abstract: A method for purifying Reb M includes preparing a crude mother liquor/Stevia rebaudiana primary extract, passing a solution of this primary extract through a multi-column system including a plurality of columns, in series, packed with a porous adsorbent resin to provide at least one column having adsorbed Reb M and eluting fractions with Reb M content from a final/last column in the series to provide an eluted solution with Reb M content.

Abstract: A method for purifying Mogroside V comprises passing a solution of a pre-prepared Siraitia grosvenori primary extract through a multi-column system including a plurality of columns, in series, packed with a porous adsorbent resin to provide at least one column having adsorbed mogrosides and eluting fractions with Mogroside V content from the at least one column having absorbed mogrosides to provide an eluted solution with Mogroside V content.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

Abstract: A sweetener composition comprises Steviol Glycoside Reb A, Steviol Glycoside Reb C, Steviol Glycoside Reb D, and at least one other secondary non-Steviol sweetener, in which Reb A has a mass percentage content of from about 0.01 to about 30.0%, Reb C has a mass percentage content of from about 0.001 to about 10.0%, and Reb D has a mass percentage content of from about 0.001 to about 10.0%, and wherein secondary non-Steviol sweetener has a mass percentage content of from about 50.0 to about 99.99%.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

Abstract: A natural sweetener composition comprises a blend of Stevioside extract and Rebaudioside A extract, wherein the ratio of Rebaudioside A extract to Stevioside extract is between about 12:1 to about 1:12 and the purity of both extracts is from about 60% to about 97.5%. The sweetener composition may further include sweet sugars and non-natural sugars.

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

Abstract: A process for producing the natural sweetener composition which comprises at least one of steviolbioside (STB) extract, Rebaudioside B extract and Rebaudioside D extract (“collectively, the “extracts”) comprises the steps of preparing a mother liquor comprising a mass content of at least 20% of at least one of the extracts; preparing feed liquid comprising at least 20 mg/mL of mother liquor; flowing feed liquid through a porous adsorption column, having a pore size of at least 40 Angstroms, a pore volume of a least 0.8 mL/g and at a flow rate of at least 1L/min and at a pH of between 4 to 5; eluting at least one steviolbioside (STB) extract, Rebaudioside B extract and Rebaudioside D extract with alcohol having a mass concentration of at least 65%; fractionally collecting one or more eluates based on chromatographic critical points for each of the steviolbioside STB extract, the Rebaudioside B extract and the Rebaudioside D extract; concentrating the extracts at a temperature of between 60-80° C.

Abstract: Natural steviol glycosides sweetener compositions comprise a blend of Rebaudioside C extract and at least one of Rebaudioside A extract and STV extract including methods for producing the same and uses thereof in foods, beverages, functional foods and nutraceuticals.

Abstract: A process for producing a natural sweetening enhancer composition comprising at least an Rebaudioside C (RC) extract, said process comprises the steps of preparing a saccharide mother liquor comprising an RC mass content of at least 15%; preparing feed liquid from about 8-25 mg/L of the mother liquor; flowing feed liquid through a porous adsorption column, having a pore size of between about 0.001 to 0.2 micron, and at a flow rate of between 25 to 35 L/m2h and at a pH of between 6 to 8; eluting RC extract with alcohol, said RC extract having a mass concentration of at least 10%; fractionally collecting eluate based on chromatographic critical point for RC extract; concentrating the RC extract and drying the extract so formed. Another process for preparing a crude RC extract which comprises the steps of preparing a saccharide mother liquor into a feedstock solution with a mass concentration of about 0.

Abstract: A substrate having a patterned mask and exposed openings is provided in a process chamber having process electrodes. In a plasma ignition stage, a process gas is provided in the process chamber and is energized by maintaining the process electrodes at a plasma ignition bias power level. In an etch-passivating stage, an etch-passivating material is formed on at least portions of the substrate by maintaining the process electrodes at an etch-passivating bias power level. In an etching stage, the exposed openings on the substrate are etched by maintaining the process electrodes at an etching bias power level.

Abstract: A substrate having a patterned mask and exposed openings is provided in a process chamber having process electrodes. In a plasma ignition stage, a process gas is provided in the process chamber and is energized by maintaining the process electrodes at a plasma ignition bias power level. In an etch-passivating stage, an etch-passivating material is formed on at least portions of the substrate by maintaining the process electrodes at an etch-passivating bias power level. In an etching stage, the exposed openings on the substrate are etched by maintaining the process electrodes at an etching bias power level.

Abstract: A substrate 20 is placed in a process zone 115 of a process chamber 110, process gas is introduced into the process zone 115, and an energized gas is formed in the process zone 115. First process conditions are set to form etch-passivating deposits onto a surface 22 of the substrate 20. Second process conditions are set to etch the surface 22 of the substrate 20. The etch-passivating deposits formed before the etching process improve etching uniformity and reduce etch-rate microloading.

Abstract: A method is provided for increasing insulin responsiveness and improving glucose tolerance in a mammal comprising administration of an effective amount of a cholinergic agonist; pharmaceutical compositions are also provided.