Abstract: Examples described herein relate to multiple processor sockets comprising processors connected thereto and first circuitry. The first circuitry is to: based on a first mode of operation: configure the multiple processor sockets to operate with a single memory address space and share interfaces and based on a second mode of operation: configure the interfaces accessible to the multiple processor sockets to provide isolated communications to processor sockets in different partitions and configure the multiple processor sockets to operate in independent memory address spaces.

Abstract: A non-feedback pre-encoder for optical DQPSK modulation includes four differential encoders, two power splitters, two delay lines, one exclusive OR gate and a cross switch. Each of two data streams input to the pre-encoder is divided into two identical streams by one of the power splitter, called an upper stream and a lower stream, respectively. Every upper stream is differentially encoded by one of the differential encoders, and outputs of the differential encoders are fed into the XOR gate. An output of the XOR gate drives the cross switch as a control signal. Two lower input data stream are delayed in the delay lines, and fed into the cross switch. The outputs of the cross switch are differentially encoded, separately, where outputs of the pre-encoder are provided. The invention eliminates the speed limitation due to the electrical propagation by constructing an all-forward control signal.

Abstract: A non-feedback pre-encoder for optical DQPSK modulation includes four differential encoders, two power splitters, two delay lines, one exclusive OR gate and a cross switch. Each of two data streams input to the pre-encoder is divided into two identical streams by one of the power splitter, called an upper stream and a lower stream, respectively. Every upper stream is differentially encoded by one of the differential encoders, and outputs of the differential encoders are fed into the XOR gate. An output of the XOR gate drives the cross switch as a control signal. Two lower input data stream are delayed in the delay lines, and fed into the cross switch. The outputs of the cross switch are differentially encoded, separately, where outputs of the pre-encoder are provided. The invention eliminates the speed limitation due to the electrical propagation by constructing an all-forward control signal.