Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

Abstract: Methods for use in electrochemical plating processes are described herein. An exemplary method includes determining a wafer electrical property associated with a wafer, wherein the wafer electrical property affects the wafer during an electrochemical plating (ECP) process; adjusting a process parameter to be applied to the wafer during the ECP process based on the determined wafer electrical property, wherein the process parameter specifies at least one of a current or a voltage; and applying the adjusted process parameter to the wafer undergoing the ECP process. In some implementations, the process parameter is adjusted, such that a peak entry current of the ECP process substantially matches a plating current of the ECP process induced following the peak entry current.

Abstract: Methods for use in electrochemical plating processes are described herein. An exemplary method includes determining a wafer electrical property associated with a wafer, wherein the wafer electrical property affects the wafer during an electrochemical plating (ECP) process; adjusting a process parameter to be applied to the wafer during the ECP process based on the determined wafer electrical property, wherein the process parameter specifies at least one of a current or a voltage; and applying the adjusted process parameter to the wafer undergoing the ECP process. In some implementations, the process parameter is adjusted, such that a peak entry current of the ECP process substantially matches a plating current of the ECP process induced following the peak entry current.

Abstract: A method for electrochemical plating includes providing a wafer for an electrochemical plating (ECP) process, determining a wafer electrical property affecting the ECP process, adjusting a plating current or voltage applied in the ECP process based on the determined wafer electrical property, and electroplating the wafer with the adjusted plating current or voltage. A controller for controlling a power supply, and a system for electrochemical plating are also disclosed.

Abstract: A method for electrochemical plating includes providing a wafer for an electrochemical plating (ECP) process, determining a wafer electrical property affecting the ECP process, adjusting a plating current or voltage applied in the ECP process based on the determined wafer electrical property, and electroplating the wafer with the adjusted plating current or voltage. A controller for controlling a power supply, and a system for electrochemical plating are also disclosed.