Abstract: Methods for removing haze defects from a photomask or reticle are disclosed. The photomask is placed into a chamber which includes a hydrogen atmosphere. The photomask is then exposed to radiation. The energy from the radiation, together with the hydrogen, causes decomposition of the haze defects. The methods can be practiced on-site and quickly, without the need for wet chemicals or the need to remove the pellicle before cleaning of the photomask. A device for conducting the methods is also disclosed herein.

Abstract: In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.

Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.

Abstract: A reflective mask includes a substrate, a lower reflective multilayer disposed over the substrate, an intermediate layer disposed over the lower reflective multilayer, an upper reflective multilayer disposed over the intermediate layer, a capping layer disposed over the upper reflective multilayer, and an absorber layer disposed in a trench formed in the upper reflective layers and over the intermediate layer. The intermediate layer includes a metal other than Cr, Ru, Si, Si compound and carbon.

Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: A solid-state storage device is provided, which includes a controller and a non-volatile memory. The controller selects a first word line group from a plurality of word line groups obtained by classifying the word lines based on a read threshold voltage of each word line, and a representative word line corresponding to each word line group is set based on the read threshold voltage associated with each word line group. The controller uses the read threshold voltage of a first representative word line corresponding to the first word line group to read page data of the first representative word line. When the controller cannot correctly read the page data of the first representative word line using the read threshold voltage of the first representative word line, the controller updates the read threshold voltage of the first representative word line in the first word line group.

Abstract: A battery charging and discharging management method. When the charging and discharging management method is implemented, an electronic device may set a lower-limit voltage of a battery to a voltage higher than a theoretical lower-limit voltage, and continuously increase the lower-limit voltage as a battery cycle passes, thereby reducing a charging/discharging volume change rate of a silicon anode as much as possible, and extending a battery life.

Abstract: A memory device is provided. The memory device includes: a write transistor, with a gate terminal connected to a write word line, and having a first source/drain terminal connected to a bit line; a storage transistor, with a gate terminal coupled to a second source/drain terminal of the write transistor to form a storage node, and having a first source/drain terminal connected to a source line; and a read transistor, with a gate terminal coupled to a read word line, and having a first source/drain terminal connected to the bit line. The read transistor and the storage transistor share a second source/drain terminal.

Abstract: A sensing method of a sense amplifier circuit is provided. The sense amplifier circuit comprises a differential amplifier. The differential amplifier comprises a first input node, a second input node, a first output node and a second output node. The sensing method comprising: providing a first switch and a second switch, wherein the first switch is coupled to the first input node and the first output node; pre-charging the first input node using a first output voltage of the first output node in response to a select signal by the first switch; and pre-charging the second input node using a second output voltage of the second output node in response to a select signal by the second switch.

Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: Methods for removing haze defects from a photomask or reticle are disclosed. The photomask is placed into a chamber which includes a hydrogen atmosphere. The photomask is then exposed to radiation. The energy from the radiation, together with the hydrogen, causes decomposition of the haze defects. The methods can be practiced on-site and quickly, without the need for wet chemicals or the need to remove the pellicle before cleaning of the photomask. A device for conducting the methods is also disclosed herein.

Abstract: A computing circuit is configured to perform a bit-serial multiplication of an input signal and a weight signal. A multiplier circuit is configured to receive the input signal and the weight signal and to provide a product sum. An adder circuit is configured to receive the product sum and to provide a partial sum. A partial sum register is configured to: clock-gate a second part of the partial sum register; receive the partial sum; provide, based on the partial sum, a first output of the bit-serial multiplication through a first part of the partial sum register; determine whether not to clock-gate the second part of the partial sum register or not based on a first feature bit of the partial sum; and provide, based on the first feature bit of the partial sum, a second output of the bit-serial multiplication through the second part of the partial sum register.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.

Abstract: A method for forming a semiconductor device structure is described. In some embodiments, the method includes forming a gate electrode, forming a mask structure over the gate electrode, patterning the mask structure to form an opening, and performing a first etch process on the gate electrode by applying a first source power and a first bias power with a first pulsing scheme. The first bias power has a first frequency to control etching along a lateral direction. The method further includes performing a second etch process on the mask structure exposed within the opening by applying a second source power and a second bias power with a second pulsing scheme, and the second bias power has a second frequency to control etching along a vertical direction. The first and second frequencies are substantially different.

Abstract: A semiconductor structure includes a substrate, an isolation structure disposed in the substrate, and a hybrid structure disposed over the isolation structure. The hybrid structure is substantially conformal with respect to a profile of the isolation structure. The hybrid structure includes an oxide component, a nitride component surrounding the oxide component, and a first polysilicon component alongside the nitride component. The nitride component includes a first upper surface closed to the first polysilicon component, and a second upper surface distal to the first polysilicon component. The second upper surface is lower than the first upper surface.

Abstract: Embodiment described herein provide systems, apparatuses and methods for convoluting a filter (“kernel”) to input data in the form of an input array by reusing computations of repeated data entries in the input array due to convolution movements from one convolution step to the next. In one embodiment, to compute a convolution of an input matrix and a filter matrix, instead of unrolling data entries from the input matrix of each convolution step into an input vector, only non-repeated new data entries at each convolution step may be added to the input vector. An input mapping circuit that implements an input parameter mapping matrix may then iteratively map data entries of the input vector to different weight registers that corresponds to weights in the filter matrix.

Abstract: An apparatus includes a process chamber, a vacuum pump disposed downstream of the process chamber for discharging a fluid flow from the process chamber, a filter mounted between the process chamber and the vacuum pump for filtering the fluid flow, and a heating device disposed to heat the filter.