Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A computation apparatus and a computation method with input swapping are provided. The computation apparatus includes a non-zero detection circuit, a swapper policy circuit, a swapper matrix circuit, and an adder tree. The non-zero detection circuit is configured to receive input vectors, inspect non-zero operands in the input vectors and generate a non-zero indicative signal indicating the non-zero operands. The swapper policy circuit is configured to receive and interpret the non-zero indicative signal, and generate multiplexer (MUX) selection signals for swapping the non-zero operands according to a set of swapping policies. The swapper matrix circuit is configured to receive the input vectors and the MUX selection signal, and perform swapping on operands in the input vectors according to the MUX selection signal. The adder tree is configured to receive the input vectors with the swapped operands and perform additions on the input vectors to output a computation result.

Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes an upper electronic structure, an upper connection structure, a first metal layer, a lower electronic structure, a lower connection structure and a second metal layer. The first metal layer electrically connects the upper electronic structure to the upper connection structure. The second metal layer electrically connects the lower electronic structure to the lower connection structure. The upper connection structure and the lower connection structure are bonded together.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.

Abstract: In a method of de-mounting a pellicle from a photo mask, the photo mask with the pellicle is placed on a pellicle holder. The pellicle is attached to the photo mask by a plurality of micro structures. The plurality of micro structures are detached from the photo mask by applying a force or energy to the plurality of micro structures before or without applying a pulling force to separate the pellicle from the photo mask. The pellicle is de-mounted from the photo mask. In one or more of the foregoing and following embodiments, the plurality of micro structures are made of an elastomer.

Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: Disclosed are a salt form used as a CDC7 inhibitor and a crystal form thereof, and specifically disclosed is a compound represented by formula (II), a crystal form thereof, a preparation method thereof, and an application thereof in the preparation of a drug for preventing or treating tumors.

Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.

Abstract: Some implementations described herein provide techniques and apparatuses for a stacked-die structure including a first integrated circuit device over a second integrated circuit device, where an operating voltage of the first integrated circuit device is different relative to an operating voltage of the second integrated circuit device. The first integrated circuit device includes a first portion of a seal ring structure of the stacked-die structure. The first portion includes an interconnect structure that connects a backside redistribution layer of the first integrated circuit device with first metal layers of the first integrated circuit device. The seal ring structure including the interconnect structure eliminates the use of diodes and electrically isolates well structures of the first integrated circuit device to reduce leakage paths relative to a stacked-die structure having a seal ring structure including a diode within the stacked-die structure.

Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack with a metal gate layer and a spacer layer disposed on a sidewall of the gate stack. In some embodiments, the method further includes performing an etch-back process to the metal gate layer to form an opening over the gate stack. In various examples, the method further includes performing a plasma treatment process to modify a profile of the opening. In some cases, the method further includes forming a HM layer over the metal gate layer and within the opening having the modified profile.

Abstract: In a method of de-mounting a pellicle from a photo mask, the photo mask with the pellicle is placed on a pellicle holder. The pellicle is attached to the photo mask by a plurality of micro structures. The plurality of micro structures are detached from the photo mask by applying a force or energy to the plurality of micro structures before or without applying a pulling force to separate the pellicle from the photo mask. The pellicle is de-mounted from the photo mask. In one or more of the foregoing and following embodiments, the plurality of micro structures are made of an elastomer.

Abstract: Some embodiments provide a process of tunning sidewall profiles of gate openings prior to filling a replacement gate electrode layer therein to improve etching rate uniformity and stability during a subsequent gate electrode etch back process. Particularly, the profile sacrificial gate electrode is adjusted to be more straight profile rather than a bowl type profile, which reduces the seam void created in the replacement gate electrode during the replacement gate process. In some embodiments, tuning the profile of gate opening further includes performing a pullback etching process of the sidewall spacers prior to depositing gate dielectric layer and work function metal layer to achieve a wider opening for metal gate filling in the replacement gate process.

Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.

Abstract: A memory device that includes a memory array and a pre-charge selecting circuit is introduced. The memory array includes a plurality of memory cells that are coupled to a plurality of bit lines and a plurality of word lines, wherein the plurality of word lines are configured to receive an input vector. The pre-charge selecting circuit is configured to selectively pre-charge a selected bit line according to a value of the input vector. The pre-charge selecting circuit is configured to determine whether the value of the input vector is less than a predefined threshold, and generate a gated pre-charge signal to skip pre-charging the selected bit line in response to determining that the value of the input vector is less than the predefined threshold.

Abstract: Embodiments include monitoring a partial sum of a multiply accumulate calculation for certain conditions. When the certain conditions are met, a reduced read energy is used to read out memory contents instead of the regular read energy used. The reduced read energy may be obtained by reducing a pre-charge voltage, withholding a pre-charge voltage or providing a ground signal, and/or by reducing voltage hold times (i.e., reducing the time a pre-charge voltage is provided and/or discharged).

Abstract: A substrate carrier, includes: a unitary body fabricated from a single block of graphite, wherein the body comprises a back plate, and a pair of spaced apart, substantially parallel, side rails, wherein each of the side rails comprises: an inwardly facing surface extending outwardly of the back plate; a longitudinally extending selenium vapor bore formed therein, a top end of the selenium vapor bore being open and configured for coupling to a selenium supply container for receiving selenium vapor by gravity, a bottom end of the selenium vapor bore being closed; an inwardly directed selenium vapor channel; a plurality of selenium vapor outlets disposed between the selenium vapor bore and the inwardly directed selenium vapor channel so as provide a plurality of conduits between the selenium vapor bore and the selenium vapor channel; and, a longitudinally extending engagement slot formed in the inwardly facing surface of each side rail adjacent the back plate to engage and hold a substrate in proximity to the ba

Abstract: A battery and an electronic device are disclosed. The battery includes: a first bare cell portion and a second bare cell portion. The first bare cell portion has a first surface and a side surface connected to the first surface, the first surface is configured to face towards a same direction as that of an opening of a battery compartment of an electronic device when the battery is installed in the battery compartment, and the side face is configured to face towards an inner side surface of the battery compartment of the electronic device when the battery is installed in the battery compartment. The second bare cell portion is located on a side that the first surface faces, and an orthographic projection of the second bare cell portion on the first surface overlaps the first surface.

Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.