Abstract: The present disclosure provides a collaborative robot arm and a joint module. The joint module includes a housing, a driving assembly, and a multi-turn absolute encoder. The joint module detects the angular position of the output shaft and records a number of rotating revolutions of the output shaft only by means of the multi-turn absolute encoder. The multi-turn absolute encoder includes a base, a bearing, a rotating shaft, an encoding disk, and a circuit board, the encoding disk is rotatably connected with the base by the rotating shaft and the bearing, the circuit board is fixedly connected with the base, and the reading head on the circuit board detects the angular position of the output shaft cooperatively with the encoding disk, making the multi-turn absolute encoder be an integrated structure. The base and the rotating shaft are detachably connected with the housing and the output shaft respectively.

Abstract: A drive structure of a desktop robotic arm is disclosed, including a base and a turntable. The base is internally provided with a turntable drive motor and a turntable drive shaft, the turntable drive motor is drive-connected to the turntable drive shaft, and the turntable drive shaft is drive-connected to the turntable. The turntable is provided with an upper arm drive motor and a forearm drive motor. The turntable drive motor, the upper arm drive motor and the forearm drive motor are all servo motors with absolute value encoders. According to the drive structure of the desktop robotic arm, by using servo motors as the drive motors for controlling the turntable, an upper arm and a forearm, for which the absolute value encoders are correspondingly configured, control accuracy and driving power can be improved. Further, the present invention also discloses a desktop robotic arm and a robot.

Abstract: An integrated joint module includes a housing, a driving assembly, a speed reduction assembly, a braking assembly and an encoding assembly. The housing includes a first housing and a second housing, an annular supporting platform is arranged on an inner side of the first housing. The driving assembly includes an output shaft, a stator embedded in the annular supporting platform, and a rotor connected with the output shaft and arranged on an inner side of the stator, the speed reduction assembly and the braking assembly are connected with two ends of the output shaft. The encoding assembly is arranged on a side of the braking assembly away from the driving assembly and connected with the output shaft, the second housing is sleeved on the encoding assembly and connected with the first housing. The integrated joint module helps to simplify the structure of the joint module and reduce the cost.

Abstract: Techniques for use in integrated circuit design systems for generation and analysis of timing characteristics associated with an integrated circuit design. In one example, a method comprises the following steps. Cells with at least one timing arc are identified from a set of cells, wherein the set of cells are useable in an integrated circuit design. A test circuit is generated comprising an input stage sub-circuit for each terminal serving as an input for each of the identified cells, and an output stage sub-circuit for each terminal serving as an output for each of the identified cells, wherein each input stage sub-circuit is independent of each other input stage sub-circuit, and each output stage sub-circuit is independent of each other output stage sub-circuit. The test circuit is stored for use in a timing delay correlation operation between a first timing analysis process and a second timing analysis process.

Abstract: Techniques for use in integrated circuit design systems for extracting noise threshold data for selected cells. For example, a method comprises the following steps. A cell is selected from one or more cells in a given collection of standardized cells. Each of the one or more cells represents one or more functional circuit design blocks that are usable as part of a design of an integrated circuit. A noise signal is generated or selected. The noise signal is applied to an input node of the selected cell. Noise threshold data is identified using a noise analysis module, for a given set of process, voltage and temperature variations, for an output node of the selected cell based on the noise signal applied to the input node of the selected cell.

Abstract: Techniques in integrated circuit design systems for generating one or more models for use in a hierarchical crosstalk noise analysis. For example, a method comprises the following steps. At least one equivalent cell noise model is generated for a circuit under modeling. The circuit under modeling comprises a plurality of cells useable in an integrated circuit design. The equivalent cell noise model is generated based on each one of the plurality of cells that have connections that terminate at ports of the circuit under modeling. The equivalent cell noise model is utilized in a hierarchical crosstalk noise analysis for the integrated circuit design.

Abstract: Techniques for use in integrated circuit design systems for extracting noise threshold data for selected cells. For example, a method comprises the following steps. A cell is selected from one or more cells in a given collection of standardized cells. Each of the one or more cells represents one or more functional circuit design blocks that are usable as part of a design of an integrated circuit. A noise signal is generated or selected. The noise signal is applied to an input node of the selected cell. Noise threshold data is identified using a noise analysis module, for a given set of process, voltage and temperature variations, for an output node of the selected cell based on the noise signal applied to the input node of the selected cell.

Abstract: Methods, systems and processor-readable media for automatic self-tracking of input deliverables for noise characterization. A noise characterization run to generate a noise model thereof can be automatically initiated. The noise model can be delivered into a repository in response to completing the noise characterization run and generating the noise model. Data associated with the noise model can be tracked for subsequent analysis including checking completeness and a correctness of the noise model delivered into the repository, The data associated with the noise model can then be rendered for the subsequent analysis. Data associated with the noise model can include, for example, information regarding pending tasks, assignment information, and data contained in a noise database.

Abstract: A methods of characterizing a regular electronic circuit and using a parameterized model of an electronic circuit to create a model for another electronic circuit. In one embodiment, the method of characterizing includes: (1) characterizing fewer than all sub-circuits associated with input and output pins of the circuit to yield data regarding the sub-circuits, (2) generating a data file containing the data, the data file constituting an expandable parameterized model of the circuit.

Abstract: A method and a tool for quickly evaluating the circuit response of VLSI designs in the presence of parasitics assists in improving VLSI designs. Offending induced voltgages are quickly identified through a simple approximation procedure, and the circuit lines where such voltages are induced are marked for evaluation with tools that make an accurate assessment. When it is determined that these circuit lines do exceed predetermined thresholds, the circuit designer is alerted to the need to redesign the circuit or its layout. The tool disclosed considers each circuit line of the VLSI circuit, and with respect to each considered circuit line, computes an estimated peak voltage due to the parasitics. The computations are very simple, involving only a summation of terms, each of which involves a quotient of one RC product by a sum of two RC products.