Abstract: An expansion cage assembly is configured to be installed onto two mounting plates, and is configured for an installation of an expansion card. The expansion cage assembly includes a supporting member, two side boards, a plurality of partitions and at least one expansion cage. The two side boards are connected to two opposite sides of the supporting member, respectively, and are detachably disposed the two mounting plates, respectively. The plurality of partitions are connected to the supporting member, and are disposed between the two side boards. The plurality of partitions are spaced apart from one another. The at least one expansion cage is disposed on one of the two side boards and the plurality of partitions.

Abstract: Base plates of a substrate retainer transportation mechanism are provided with damping members to assist elastic members in damping and limiting movement of the substrate retainer transportation mechanism when the substrate transportation mechanism is subjected to unwanted external forces, e.g., seismic forces. By damping and limiting movement of the substrate retainer transportation mechanism, undesirable damage to substrates contained in a substrate retainer being carried by the substrate retainer transport mechanism can be minimized.

Abstract: A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Abstract: A plasma etching system generates a plasma above a wafer in a plasma etching chamber. The wafer is surrounded by a focus ring. The plasma etching system straightens a plasma sheath above the focus ring by generating a supplemental electric field above the focus ring.

Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer on the substrate; isolation structures extending through the dielectric layer into the substrate; and a floating gate on the dielectric layer and between the isolation structures, wherein the floating gate includes a first portion directly on the dielectric layer; and second portions on the sidewalls of the first portion.

Abstract: In a method of controlling a plasma beam of a plasma etcher a flow rate controller of the plasma etcher is set to generate one or more flow rates of an etching gas corresponding to one or more plasma beams of the plasma etcher. The emitted light generated by plasma discharge corresponding to the one or more plasma beams of the plasma etcher is monitored. The flow rate controller is calibrated based on the one or more flow rates and a corresponding emitted light of the plasma discharge.

Abstract: A system and method for generating a gas curtain over an access port of a processing chamber for a semiconductor substrate. A gas flow stabilizer and a gas flow receiver, each including a horizontal flow section and a vertical flow section cooperate to generate a gas curtain that impedes gas, e.g., oxygen, from outside the processing chamber, from flowing into the chamber, for example, when the access port is opened to add/or to remove a workpiece from the processing chamber.

Abstract: In a method of controlling a plasma beam of a plasma etcher a flow rate controller of the plasma etcher is set to generate one or more flow rates of an etching gas corresponding to one or more plasma beams of the plasma etcher. The emitted light generated by plasma discharge corresponding to the one or more plasma beams of the plasma etcher is monitored. The flow rate controller is calibrated based on the one or more flow rates and a corresponding emitted light of the plasma discharge.

Abstract: A chamber for a physical vapor deposition (PVD) apparatus includes a collimator configured to narrow filter sputtered particles into a beam, an electrostatic chuck configured to support a substrate in the chamber, a shield and a chamber plate. The chamber plate includes a nut plate portion having a plurality of nut plates and a plurality of cavities in the chamber plate that are configured to allow gas to ingress and egress, wherein the cavities and nut plates are provided in equal numbers. The chamber is configured to operate at a target pressure, and the number of nut plates and corresponding number of cavities are determined based on the target pressure.

Abstract: When performing full firmware update procedure on an electronic device, a full firmware update file is divided into multiple pieces of update data and then arranged into a first and a second sub update files, a header file associated with the sizes of each sub update file is created, and the header file and the two sub update files are merged into a full FOTA file before being uploaded to the electronic device. The electronic device extracts each sub update file based on the header file and stores the extracted first and second sub update file respectively into a first and a second storage units. After performing the firmware update steps associated with the first sub update file, the second sub update file stored in the second storage unit is copied to the first storage unit before performing the firmware update steps associated with the second sub update file.

Abstract: The present disclosure provides an artificial leather structure, comprising a woven layer, a porous elastomer layer disposed on the woven layer and a nonwoven layer disposed on the porous elastomer layer. The porous elastomer layer is adhered to the woven layer and the nonwoven layer.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A chamber for a physical vapor deposition (PVD) apparatus includes a collimator configured to narrow filter sputtered particles into a beam, an electrostatic chuck configured to support a substrate in the chamber, a shield and a chamber plate. The chamber plate includes a nut plate portion having a plurality of nut plates and a plurality of cavities in the chamber plate that are configured to allow gas to ingress and egress, wherein the cavities and nut plates are provided in equal numbers. The chamber is configured to operate at a target pressure, and the number of nut plates and corresponding number of cavities are determined based on the target pressure.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: Disclosed is a flip-chip packaged power transistor module having a built-in gate driver, for outputting a high-power signal of at least tens of amperes, the module including at least one power transistor die which has an active side where at least one source pin, at least one drain pin and at least one gate pin are exposed; a ceramic substrate body which has a conducting junction side and a heat spreading side, a minimal spacing of the gate bonding pad from at least one of the source bonding pad or the drain bonding pad being less than 500 ?m, whereby parasitic inductance generated therebetween is reduced; at least one gate driver which has at least one gate pin configured to be soldered to the gate bonding pad, and at least one gate drive pin which corresponds to the gate pin and is configured to be soldered to the drive bonding pad.

Abstract: In example implementations, an apparatus is provided. The apparatus includes an interface, a graphics card connected to the interface, and a controller communicatively coupled to the interface. The graphics card includes an air moving device. The controller is to send a logic control to the graphics card to activate the air moving device in response to a performance parameter.