Abstract: A method includes loading a wafer over a wafer chuck in a process chamber; performing a deposition process on the loaded wafer; supplying a fluid medium to a fluid guiding structure in the wafer chuck from a fluid inlet port on the wafer chuck, the fluid guiding structure comprising a plurality of arc-shaped channels fluidly communicated with each other; guiding the fluid medium from a first one of the arc-shaped channels of the fluid guiding structure to a second one of the arc-shaped channels of the fluid guiding structure. The second one of the arc-shaped channels of the fluid guiding structure is concentric with the first one of the arc-shaped channels of the fluid guiding structure from a top view.

Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Abstract: An integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. The transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. A gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.

Abstract: A display panel includes a substrate and a plurality of pixel structures disposed on the substrate. Each of the pixel structures includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element is disposed on the substrate and configured to generate a first colored light. A light output surface of the first light-emitting element includes a combined region. The second light-emitting element is disposed on a part of the combined region and configured to generate a second colored light. The third light-emitting element is disposed on the other part of the combined region and configured to generate a third colored light.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: The driving circuit of the display includes a timing controller. The timing controller is coupled to a general purpose input/output (GPIO) pin of the touch driver. The timing controller receives an instruction signal via the GPIO pin of the touch driver. The timing controller starts a detection period according to a first edge switched from a first voltage level to a second voltage level of the instruction signal. The timing controller detects a number of pulse signals of the instruction signal, and determines a current operating status of the touch driver according to the number of pulse signals of the instruction signal during the detection period. The timing controller determines that the current operating status of the touch driver is one of touch operation type statuses according to the number of pulse signals of the instruction signal during the detection period being a default number.

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

Abstract: The present disclosure is related to a touchpad structure, which includes a cover plate, a backlight unit, a touch circuit layer, a first optical modulation layer, and a second optical modulation layer. The first optical modulation layer is disposed between the cover plate and the backlight unit, and having a first reflectivity. The second optical modulation layer is disposed between the first optical modulation layer and the touch circuit layer. The second optical modulation layer has a second reflectivity and a first penetration rate, wherein the second reflectivity is the same as the first reflectivity, or the first reflectivity is the same as the first penetration rate. The touchpad structure can present a uniform color spectrum via the second optical modulation layer and the first optical modulation layer.

Abstract: A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapping around the first nanostructures. The structure also includes a first source/drain epitaxial structure formed beside the first nanostructures. The structure also includes a first inner spacer between the first gate structure and the first source/drain epitaxial structure. The structure also includes second nanostructures formed over the first nanostructure. The structure also includes a second gate structure wrapping around the second nanostructures. The structure also includes a second source/drain epitaxial structure formed beside the second nanostructures. The structure also includes a second inner spacer between the second gate structure and the second source/drain epitaxial structure. A sidewall of the second inner spacer is spaced apart from a sidewall of the first inner spacer when viewed from above.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: A circuit structure includes a light-transmissive insulation layer, a patterned conductive layer and an electronic component. The patterned conductive layer is disposed on the light-transmissive insulation layer. The electronic component is disposed on the patterned conductive layer and electrically connected to the patterned conductive layer.

Abstract: An electrophoretic display device includes a substrate, an electrophoretic display film, a plurality of second electrodes, and a plurality of third electrodes. The electrophoretic display film is disposed on the substrate and includes a display medium layer and a first electrode. The second electrodes and the third electrodes are disposed on the substrate and located between the display medium layer and the substrate. A first voltage received by each of the second electrodes is controlled by a corresponding thin-film transistor. The third electrodes and the second electrodes are alternately disposed in a direction. The first voltage is different from a second voltage received by the third electrodes.

Abstract: A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.

Abstract: A process used to form a first deep trench isolation (DTI) structure in a pixel region of a semiconductor substrate is also used to form a second DTI structure in a guard ring area that isolates the pixel region from a peripheral region. The guard ring area may have a PNP guard ring structure. The second DTI structure may include trenches in each of an inner ring, a middle, and an outer ring of the PNP guard ring structure. The first and second DTI structures may have conductive cores. The conductive cores of the inner and outer ring may be biased to a first voltage while the conductive cores of the middle ring may be biased to an opposite polarity second voltage. When the second DTI structure have conductive cores with these biases, the second DTI structure may be used as the guard ring without the PNP structure.

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.