Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.

Abstract: A growth method for reducing defect density of GaN includes steps of: sequentially forming a buffer growth layer, a stress release layer and a first nanometer cover layer on a substrate, wherein the first nanometer cover layer has multiple openings interconnected with the stress release layer; growing a first island in each of the openings; growing a first buffer layer and a second nanometer cover layer on the first island; and growing a second island to form a dislocated island structure. Thus, through the first nanometer cover layer and the second nanometer cover layer, multiple dislocated island structures can be directly formed to reduce manufacturing complexity as well as increase yield rate by decreasing manufacturing environment variation. Further, the epitaxial lateral over growth (ELOG) approach also effectively enhances characteristics of GaN optoelectronic semiconductor elements.