Patents by Inventor Lung-Ching Kao

Lung-Ching Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9406745
    Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 2, 2016
    Assignee: PFC DEVICE HOLDINGS LIMITED
    Inventors: Paul Chung-Chen Chang, Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao
  • Patent number: 9379180
    Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: June 28, 2016
    Assignee: PFC DEVICE HOLDINGS LIMITED
    Inventors: Paul Chung-Chen Chang, Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao
  • Publication number: 20150325643
    Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
    Type: Application
    Filed: July 23, 2015
    Publication date: November 12, 2015
    Inventors: Paul Chung-Chen CHANG, Kuo-Liang CHAO, Mei-Ling CHEN, Lung-Ching KAO
  • Patent number: 8982524
    Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 17, 2015
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
  • Patent number: 8963296
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 24, 2015
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Publication number: 20140217561
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 7, 2014
    Applicant: VISHAY GENERAL SEMICONDUCTOR, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Publication number: 20140167205
    Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: PFC DEVICE HOLDINGS LIMITED
    Inventors: Paul Chung-Chen CHANG, Kuo-Liang CHAO, Mei-Ling CHEN, Lung-Ching KAO
  • Patent number: 8753963
    Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: June 17, 2014
    Assignee: PFC Device Corp.
    Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
  • Patent number: 8704298
    Abstract: A MOS diode includes a substrate with a mesa, a P-type semiconductor region with etched shallow trench surrounding the mesa, that cause an increasing metal contact area to reduce Vf value, a gate oxide layer arranged on the mesa, a polysilicon layer arranged on the gate oxide layer, and a shielding oxide layer arranged on the polysilicon layer. The termination structure includes a trench, an oxide layer arranged at least within the trench, at least one sidewall polysilicon layer arranged on the oxide layer within the trench. In the MOS diode, the shielding oxide layer is thicker than the gate oxide layer to prevent leaking current. The oxide layer and the sidewall polysilicon layer can enhance the reverse voltage tolerance of the MOS diode. A metal layer covers the polysilicon region, shielding oxide layer, semiconductor regions with etched shallow trench, termination region and some parts outside the termination region.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 22, 2014
    Assignee: PFC Device Corp.
    Inventors: Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao, Hung-Hsin Kuo
  • Patent number: 8680590
    Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: March 25, 2014
    Assignee: PFC Device Corp.
    Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
  • Patent number: 8643152
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: February 4, 2014
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Publication number: 20140030882
    Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 30, 2014
    Applicant: PFC DEVICE CORP.
    Inventors: Lung-Ching KAO, Mei-Ling CHEN, Kuo-Liang CHAO, Hung-Hsin KUO
  • Publication number: 20130228891
    Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
  • Patent number: 8461646
    Abstract: A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 11, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventor: Lung-Ching Kao
  • Publication number: 20120223421
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Application
    Filed: February 27, 2012
    Publication date: September 6, 2012
    Applicant: VISHAY GENERAL SEMICONDUCTOR, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Publication number: 20120200975
    Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 9, 2012
    Applicant: Vishay General Semiconductor, LLC
    Inventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
  • Publication number: 20120199902
    Abstract: A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 9, 2012
    Applicant: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventor: Lung-Ching Kao
  • Patent number: 8125056
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: February 28, 2012
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8111495
    Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: February 7, 2012
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
  • Patent number: 8014117
    Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: September 6, 2011
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu