Patents by Inventor Lung-Ching Kao
Lung-Ching Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9406745Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.Type: GrantFiled: July 23, 2015Date of Patent: August 2, 2016Assignee: PFC DEVICE HOLDINGS LIMITEDInventors: Paul Chung-Chen Chang, Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao
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Patent number: 9379180Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.Type: GrantFiled: December 12, 2013Date of Patent: June 28, 2016Assignee: PFC DEVICE HOLDINGS LIMITEDInventors: Paul Chung-Chen Chang, Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao
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Publication number: 20150325643Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.Type: ApplicationFiled: July 23, 2015Publication date: November 12, 2015Inventors: Paul Chung-Chen CHANG, Kuo-Liang CHAO, Mei-Ling CHEN, Lung-Ching KAO
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Patent number: 8982524Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.Type: GrantFiled: February 6, 2012Date of Patent: March 17, 2015Assignee: Vishay General Semiconductor, LLCInventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
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Patent number: 8963296Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: GrantFiled: January 31, 2014Date of Patent: February 24, 2015Assignee: Vishay General Semiconductor, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Publication number: 20140217561Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: ApplicationFiled: January 31, 2014Publication date: August 7, 2014Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Publication number: 20140167205Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: PFC DEVICE HOLDINGS LIMITEDInventors: Paul Chung-Chen CHANG, Kuo-Liang CHAO, Mei-Ling CHEN, Lung-Ching KAO
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Patent number: 8753963Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: GrantFiled: September 26, 2013Date of Patent: June 17, 2014Assignee: PFC Device Corp.Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
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Patent number: 8704298Abstract: A MOS diode includes a substrate with a mesa, a P-type semiconductor region with etched shallow trench surrounding the mesa, that cause an increasing metal contact area to reduce Vf value, a gate oxide layer arranged on the mesa, a polysilicon layer arranged on the gate oxide layer, and a shielding oxide layer arranged on the polysilicon layer. The termination structure includes a trench, an oxide layer arranged at least within the trench, at least one sidewall polysilicon layer arranged on the oxide layer within the trench. In the MOS diode, the shielding oxide layer is thicker than the gate oxide layer to prevent leaking current. The oxide layer and the sidewall polysilicon layer can enhance the reverse voltage tolerance of the MOS diode. A metal layer covers the polysilicon region, shielding oxide layer, semiconductor regions with etched shallow trench, termination region and some parts outside the termination region.Type: GrantFiled: March 14, 2013Date of Patent: April 22, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao, Hung-Hsin Kuo
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Patent number: 8680590Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: GrantFiled: March 2, 2012Date of Patent: March 25, 2014Assignee: PFC Device Corp.Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
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Patent number: 8643152Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: GrantFiled: February 27, 2012Date of Patent: February 4, 2014Assignee: Vishay General Semiconductor, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Publication number: 20140030882Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Applicant: PFC DEVICE CORP.Inventors: Lung-Ching KAO, Mei-Ling CHEN, Kuo-Liang CHAO, Hung-Hsin KUO
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Publication number: 20130228891Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: ApplicationFiled: March 2, 2012Publication date: September 5, 2013Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
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Patent number: 8461646Abstract: A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.Type: GrantFiled: February 4, 2011Date of Patent: June 11, 2013Assignee: Vishay General Semiconductor LLCInventor: Lung-Ching Kao
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Publication number: 20120223421Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: ApplicationFiled: February 27, 2012Publication date: September 6, 2012Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Publication number: 20120200975Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.Type: ApplicationFiled: February 6, 2012Publication date: August 9, 2012Applicant: Vishay General Semiconductor, LLCInventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
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Publication number: 20120199902Abstract: A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.Type: ApplicationFiled: February 4, 2011Publication date: August 9, 2012Applicant: VISHAY GENERAL SEMICONDUCTOR LLCInventor: Lung-Ching Kao
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Patent number: 8125056Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: GrantFiled: September 23, 2009Date of Patent: February 28, 2012Assignee: Vishay General Semiconductor, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Patent number: 8111495Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.Type: GrantFiled: June 20, 2007Date of Patent: February 7, 2012Assignee: Vishay General Semiconductor, LLCInventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
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Patent number: 8014117Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.Type: GrantFiled: June 20, 2007Date of Patent: September 6, 2011Assignee: Vishay General Semiconductor, LLCInventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu