Patents by Inventor Lung Shih
Lung Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002771Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.Type: GrantFiled: May 13, 2021Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lung Shih, Chao-Keng Li, Alan Kuo, C. C. Chang, Yi-An Lin
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Publication number: 20240079357Abstract: An integrated circuit (IC) device includes a redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range. The IC device further includes a passivation layer over the redistribution line, wherein a bottommost surface of the passivation layer is below the bottommost surface of the redistribution line.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Yi-An LIN, Alan KUO, C. C. CHANG, Yu-Lung SHIH
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Patent number: 11817404Abstract: An integrated circuit (IC) device includes a redistribution line over a substrate, wherein an entire sidewall of the redistribution line is curved. The IC device further includes a passivation layer over the redistribution line, wherein a distance from a bottommost surface of the passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate. The IC device further includes a polymer layer over the passivation layer.Type: GrantFiled: August 5, 2021Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-An Lin, Alan Kuo, C. C. Chang, Yu-Lung Shih
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Publication number: 20230339200Abstract: A midsole molding method includes the following steps: creating an upper surface model of a midsole based on a personalized foot information and a human factor information; installing or forming the upper surface model on a bottom of the production mold; and placing the upper surface model inside a sole mold, to form the midsole between the upper surface model and the sole mold. Through the above molding method, the midsole can have ergonomic designs to have the support of insoles, to rectify the gait, or to relieve partial pressure etc. The disclosure can offer a foot-improving effect without the need to place insoles inside the shoe.Type: ApplicationFiled: October 5, 2022Publication date: October 26, 2023Inventors: Min-Chih SHIH, Cheng-Yu SHIH, Cheng-Lung SHIH
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Publication number: 20230200088Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer.Type: ApplicationFiled: February 23, 2023Publication date: June 22, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 11621296Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.Type: GrantFiled: April 6, 2021Date of Patent: April 4, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 11599988Abstract: A target image of a target circuit board and a gold image of a gold circuit board are taken by an image acquisition system. Fiducial points are located on the target image and on the gold image. Perspective transformation is performed on the target image using the fiducial points on the target image for reference and on the gold image using the fiducial points on the gold image for reference. After perspective transformation, an anomalous section of the target image is identified by identifying pixels that have different intensities between the target image and the gold image, the anomalous section being indicative of an unauthorized modification to the target circuit board.Type: GrantFiled: September 11, 2020Date of Patent: March 7, 2023Assignee: Super Micro Computer, Inc.Inventors: Bo-Han Wo, Chun-Yi Lin, Yu-Lung Shih, Kai Cheng Wen, Kevin Wei-Chou Chen, Yu-Jung Liang, Pei Hsiang Yang, Jenn-Chih Chou
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Publication number: 20230051000Abstract: A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.Type: ApplicationFiled: October 5, 2021Publication date: February 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ang Chan, Hsin-Jung Liu, Kun-Ju Li, Chau-Chung Hou, Fu-Shou Tsai, Yu-Lung Shih, Jhih-Yuan Chen, Chun-Han Chen, Wei-Xin Gao, Shih-Ming Lin
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Publication number: 20220310461Abstract: An in-wafer testing device for a wafer apparatus includes a testing wafer and a testing circuit. The testing wafer is adapted to be put into the wafer apparatus. The testing circuit is integrated in the testing wafer, and configured to measure one or more properties of the wafer apparatus.Type: ApplicationFiled: March 24, 2021Publication date: September 29, 2022Inventors: Te-Lung SHIH, Chao-Feng HSU
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Publication number: 20220084878Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.Type: ApplicationFiled: September 17, 2020Publication date: March 17, 2022Inventors: Fu-Shou Tsai, Yang-Ju Lu, Yong-Yi Lin, Yu-Lung Shih, Ching-Yang Chuang, Ji-Min Lin, Kun-Ju Li
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Publication number: 20220084174Abstract: A target image of a target circuit board and a gold image of a gold circuit board are taken by an image acquisition system. Fiducial points are located on the target image and on the gold image. Perspective transformation is performed on the target image using the fiducial points on the target image for reference and on the gold image using the fiducial points on the gold image for reference. After perspective transformation, an anomalous section of the target image is identified by identifying pixels that have different intensities between the target image and the gold image, the anomalous section being indicative of an unauthorized modification to the target circuit board.Type: ApplicationFiled: September 11, 2020Publication date: March 17, 2022Applicant: Super Micro Computer, Inc.Inventors: Bo-Han WO, Chun-Yi LIN, Yu-Lung SHIH, Kai Cheng WEN, Kevin Wei-Chou CHEN, Yu-Jung LIANG, Pei Hsiang YANG, Jenn-Chih CHOU
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Patent number: 11257711Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.Type: GrantFiled: September 17, 2020Date of Patent: February 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yang-Ju Lu, Yong-Yi Lin, Yu-Lung Shih, Ching-Yang Chuang, Ji-Min Lin, Kun-Ju Li
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Patent number: 11211471Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.Type: GrantFiled: September 10, 2020Date of Patent: December 28, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Shou Tsai, Yong-Yi Lin, Yang-Ju Lu, Yu-Lung Shih, Ji-Min Lin, Ching-Yang Chuang, Kun-Ju Li
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Publication number: 20210375802Abstract: An integrated circuit (IC) device includes a redistribution line over a substrate, wherein an entire sidewall of the redistribution line is curved. The IC device further includes a passivation layer over the redistribution line, wherein a distance from a bottommost surface of the passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate. The IC device further includes a polymer layer over the passivation layer.Type: ApplicationFiled: August 5, 2021Publication date: December 2, 2021Inventors: Yi-An LIN, Alan KUO, C. C. CHANG, Yu-Lung SHIH
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Patent number: 11145602Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.Type: GrantFiled: February 10, 2020Date of Patent: October 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Jhih-Yuan Chen, Hsin-Jung Liu, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Fu-Chun Hsiao, Ji-Min Lin, Chun-Han Chen
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Patent number: 11114395Abstract: An integrated circuit (IC) device includes a first passivation layer over a substrate. The IC device further includes a redistribution line over the first passivation layer, wherein the redistribution line has a barrel-shaped profile. The IC device further includes a second passivation layer over the redistribution line. The IC device further includes a polymer layer over the second passivation layer.Type: GrantFiled: October 21, 2019Date of Patent: September 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-An Lin, Alan Kuo, C. C. Chang, Yu-Lung Shih
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Publication number: 20210265292Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.Type: ApplicationFiled: May 13, 2021Publication date: August 26, 2021Inventors: Yu-Lung SHIH, Chao-Keng LI, Alan KUO, C. C. CHANG, Yi-An LIN
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Publication number: 20210249357Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Inventors: Kun-Ju Li, Jhih-Yuan Chen, Hsin-Jung Liu, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Fu-Chun Hsiao, Ji-Min Lin, Chun-Han Chen
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Publication number: 20210225932Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 11018100Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device includes a dielectric layer over the conductive pad, wherein the dielectric layer comprises silicon oxide. The semiconductor device includes a first passivation layer directly over the dielectric layer, wherein the first passivation layer comprises silicon oxide. The semiconductor device includes a second passivation layer directly over the first passivation layer, wherein the second passivation layer comprises silicon nitride.Type: GrantFiled: May 13, 2019Date of Patent: May 25, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lung Shih, Chao-Keng Li, Alan Kuo, C. C. Chang, Yi-An Lin