Abstract: A single chip replacement upgradeable/downgradeable data processing system capable of operating with different types of central processing unit (CPU) chips. The system has a first socket for registration of a first CPU chip and a second socket for registration of a second CPU chip. Circuitry is provided for preventing possible signal contention between the first and second CPU chips and for synchronizing clocks for operating a CPU with the system clock. Circuitry is also provided for interfacing with a coprocessor associated with the different types of CPU chips as well as for adjusting the signals to and from the CPU chips to the signal width of the system.

Abstract: An upgradeable/downgradeable computer system is made capable of being driven by more than one model of central processing units, including at least one socket means capable of being plugged with different model of central processing units, an identifying circuit capable of identifying the model of the central processing unit in the socket means and generating an identifying signal, a clock generator responsive to the identifying signal for generating a clock signal acceptable to the model of the central processing unit in the socket means, and a means responsive to the identifying signal for gating and inhibiting a plurality of input/output signals of the central processing unit in the socket means.