Patents by Inventor Lung Yi Kuo
Lung Yi Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9471485Abstract: A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.Type: GrantFiled: June 25, 2013Date of Patent: October 18, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Han-Sung Chen
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Patent number: 9152557Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.Type: GrantFiled: April 30, 2014Date of Patent: October 6, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Shuo-Nan Hung, Han-Sung Chen
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Patent number: 8947961Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.Type: GrantFiled: July 25, 2013Date of Patent: February 3, 2015Assignee: Macronix International Co., Ltd.Inventors: Lung Yi Kuo, Hsin Yi Ho, Chun Hsiung Hung, Shuo-Nan Hung, Han-Sung Chen, Shih-Chou Juan
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Publication number: 20140269074Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.Type: ApplicationFiled: July 25, 2013Publication date: September 18, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Lung Yi KUO, Hsin Yi Ho, Chun Hsiung Hung, Shuo-Nan Hung, Han-Sung Chen, Shih-Chou Juan
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Publication number: 20140281175Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.Type: ApplicationFiled: April 30, 2014Publication date: September 18, 2014Applicant: Macronix International Co., Ltd.Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Shuo-Nan Hung, Han-Sung Chen
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Publication number: 20140281150Abstract: A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.Type: ApplicationFiled: June 25, 2013Publication date: September 18, 2014Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Han-Sung Chen
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Patent number: 8738844Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.Type: GrantFiled: April 14, 2011Date of Patent: May 27, 2014Assignee: Macronix International Co., Ltd.Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Shuo-Nan Hung, Han-Sung Chen
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Publication number: 20120265923Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Shuo-Nan Hung, Han-Sung Chen
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Publication number: 20110072333Abstract: A control method for flash memory based on variable length ECC is provided in the present invention. A first channel of the flash memory is set to have a first ECC with a first length based on the size of data page and the length of first management data; and a second channel of the flash memory is set to have a second ECC with a second length based on the size of data page and the length of second management data. The first ECC and the second ECC are designated with different identification codes respectively, wherein the first length is shorter than the second length.Type: ApplicationFiled: September 24, 2009Publication date: March 24, 2011Applicant: INNOSTOR TECHNOLOGY CORPORATIONInventor: Lung-Yi KUO
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Patent number: 7748044Abstract: A system for processing DRM-enabled files includes a playback device and a software module. The software module includes a license-downloading module, a license-transforming module, a decryption module and an encryption module. The license-downloading module is configured to download a first license from a license server to a computer. The license-transforming module is configured to convert the first license to a second license. The decryption module is configured to decrypt a first DRM-enabled file of the computer into a raw file with a first decryption key. The encryption module is configured to encrypt the raw file into a second DRM-enabled file with a second encryption key. The playback device is configured to decrypt the second DRM-enabled file with the second license. The method of the system is also provided.Type: GrantFiled: August 11, 2006Date of Patent: June 29, 2010Assignee: Siliconmotion Inc.Inventors: Lung-Yi Kuo, Shin-Ping Lin, Chun-Ching Huang
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Patent number: 7617353Abstract: The present invention provides a flash memory circuit for accessing an IDE apparatus. This flash memory circuit includes a flash memory controller, a latch circuit and an IDE apparatus. The flash memory controller outputs a latch signal to control the latch circuit to access a special address signal and output a RD/WR signal. The RD/WR signal is used to access data from the IDE apparatus according to the special address signal.Type: GrantFiled: January 19, 2006Date of Patent: November 10, 2009Assignee: Silicon Motion Inc.Inventors: Lung-Yi Kuo, Yung-Hao Chang
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Publication number: 20070168599Abstract: The present invention provides a flash memory circuit for accessing an IDE apparatus. This flash memory circuit includes a flash memory controller, a latch circuit and an IDE apparatus. The flash memory controller outputs a latch signal to control the latch circuit to access a special address signal and output a RD/WR signal. The RD/WR signal is used to access data from the IDE apparatus according to the special address signal.Type: ApplicationFiled: January 19, 2006Publication date: July 19, 2007Inventors: Lung-Yi Kuo, Yung-Hao Chang
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Publication number: 20070162977Abstract: A system for processing DRM-enabled files includes a playback device and a software module. The software module includes a license-downloading module, a license-transforming module, a decryption module and an encryption module. The license-downloading module is configured to download a first license from a license server to a computer. The license-transforming module is configured to convert the first license to a second license. The decryption module is configured to decrypt a first DRM-enabled file of the computer into a raw file with a first decryption key. The encryption module is configured to encrypt the raw file into a second DRM-enabled file with a second encryption key. The playback device is configured to decrypt the second DRM-enabled file with the second license. The method of the system is also provided.Type: ApplicationFiled: August 11, 2006Publication date: July 12, 2007Inventors: Lung-Yi Kuo, Shin-Ping Lin, Chun-Ching Huang
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Publication number: 20070050534Abstract: A method for supporting an unrecognizable flash memory, at least including steps of sending a parameter table comprising strings for error checking to a specified address, checking if the identification is unknown, reading the specified address in the flash memory to determine its cycle if the identification is unknown, checking if the strings for error checking are correctly read, and accessing the system code of the flash memory.Type: ApplicationFiled: November 18, 2005Publication date: March 1, 2007Applicant: SILICONMOTION INC.Inventors: Lung-Yi Kuo, Sheng-I Hsu
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Patent number: 7137037Abstract: A method for testing a data storage system. The data storage system contains a buffer area, firmware and a storage area. The method including: selecting at least one product testing item, commanding the firmware to execute a starting process in order to transfer the storage system from general working mode to testing mode, commanding the firmware to execute a testing process corresponding to the selected product testing item, the executed testing process generates a testing result, displaying the result; and commanding the firmware to execute an ending process in order to return the storage to general working mode. Users use an application program to give commands to the firmware after requesting disc access service from the computer operation system. The buffer area can be a RAM (Random Access Memory). The testing result can be displayed on a computer monitor.Type: GrantFiled: March 27, 2003Date of Patent: November 14, 2006Assignee: Silicon Motion, Inc.Inventors: Lung Yi Kuo, Yu-Ling How
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Publication number: 20040194062Abstract: A method for testing data storage system. The data storage system contains a buffer area, a firmware and a storage area. The method including: selecting at least a product testing item, commanding the firmware to execute a starting process in order the storage system transferred from general working mode to testing mode, commanding the firmware to execute a testing process corresponding to the selected product testing item, the executed testing process generates a testing result, displaying the result; and commending the firmware to execute an ending process in order the storage returns to general working mode. Users use an application program to give commands to the firmware after requesting disc access service from the computer operation system. The buffer area can be a RAM (Random Access Memory). The testing result can be displayed on a computer monitor.Type: ApplicationFiled: March 27, 2003Publication date: September 30, 2004Inventors: Lung Yi Kuo, Yu-Ling How
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Patent number: 6754756Abstract: A global positioning system (GPS) card reader comprises a bus connection interface, a GPS module, a universal asynchronous receiver transmitter (UART) coupled with the GPS module and a complex programmable logic circuit comprising a complex programmable logic device. The complex programmable logic circuit connects with the bus connection interface and comprises at least: a card information structural (CIS) memory, am address decoder, a power control register, and a storage card coupling for connecting a storage card.Type: GrantFiled: August 8, 2001Date of Patent: June 22, 2004Assignee: Feiya Technology Corp.Inventors: Cheng-Chih Chien, Bing-Fei Wu, Jou-Wei Fu, Lung-Yi Kuo, Chung-Chi Tien
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Publication number: 20030204737Abstract: A method is provided for secreting a disk drive and keeping it portable, in which the disk drive is connected with a host computer via a USB interface and comprises at least a microprocessor and a memory unit storing a state parameter and a preset code.Type: ApplicationFiled: April 25, 2002Publication date: October 30, 2003Inventors: Chee-Horng Lee, Lung-Yi Kuo, Yung-Hao Chang
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Publication number: 20030033465Abstract: A hot-swap device applicable to the ATA interface comprises at least an integrated drive electronics (IDE) hard disk drive controller for processing IDE instructions transferred from the ATA interface, wherein at least a program code is provided to the IDE hard disk drive controller for the same to execute and respond to the ATA interface “a virtual storage device” in the case of lacking a real storage device connected to the IDE hard disk drive controller directly or via the ATA interface, or if a “real storage device” is connected with the IDE hard disk drive directly or via the ATA interface, the ATA interface will receive response from the “real storage device”.Type: ApplicationFiled: August 8, 2001Publication date: February 13, 2003Inventors: Cheng-Chih Chien, Being-Fei Wu, Jou-Wei Fu, Lung-Yi Kuo, Sheng-I Hsu, Chung-Chi Tien
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Publication number: 20030033462Abstract: A global positioning system (GPS) card reader comprises a bus connection interface, a GPS module, a universal asynchronous receiver transmitter (UART) coupled with the GPS module and a complex programmable logic circuit comprising a complex programmable logic device. The complex programmable logic circuit connects with the bus connection interface and comprises at least: a card information structural (CIS) memory, am address decoder, a power control register, and a storage card coupling for connecting a storage card.Type: ApplicationFiled: August 8, 2001Publication date: February 13, 2003Inventors: Cheng-Chih Chien, Bing-Fei Wu, Jou-Wei Fu, Lung-Yi Kuo, Chung-Chi Tien