Patents by Inventor Lung-Yuan Wang
Lung-Yuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11973047Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.Type: GrantFiled: November 24, 2020Date of Patent: April 30, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Feng Kao, Lung-Yuan Wang
-
Publication number: 20240055402Abstract: An electronic package is provided, in which a stacking component and a plurality of conductive pillars are embedded in a packaging layer, and a routing structure is formed on the packaging layer, where the stacking component is formed by stacking a first electronic module and a second electronic module on each other, and a plurality of first conductive vias and a plurality of second conductive vias are served as the electrical connection paths between the first electronic module and the second electronic module, such that the transmission distance of electrical signals between a first electronic element in the first electronic module and a second electronic element in the second electronic module can be reduced.Type: ApplicationFiled: December 8, 2022Publication date: February 15, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Lung-Yuan WANG, Feng KAO, Chiu-Ling CHEN, Hung-Kai WANG
-
Publication number: 20230420391Abstract: An electronic package is provided, in which an electronic element that is electrically connected to a plurality of conductive vias and a functional part that has a hollow area are disposed on a photonic die that has the plurality of conductive vias and at least one external connection portion, where a cladding layer covers the electronic element and the functional part, such that the external connection portion is exposed from the hollow area and the cladding layer for an optical fiber to insert into the hollow area and connect to the external connection portion, so as to achieve the purpose of optoelectronic integration.Type: ApplicationFiled: September 14, 2022Publication date: December 28, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Feng Kao, Lung-Yuan Wang
-
Publication number: 20230369229Abstract: An electronic package and manufacturing method thereof are provided, in which an electronic module served as a bridge element and a plurality of conductive pillars are embedded in a packaging layer, a routing structure is formed on the packaging layer, and a plurality of electronic elements are disposed on the routing structure, such that the electronic elements electrically bridge the electronic module via the routing structure.Type: ApplicationFiled: July 6, 2022Publication date: November 16, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Hsin-Jou Lin, Lung-Yuan Wang, Chih-Nan Lin, Feng Kao, Chiu-Ling Chen
-
Publication number: 20230260886Abstract: An electronic package is provided, in which a circuit structure is disposed on the uppermost side of a plurality of stacked organic material substrates for connecting an electronic element, so that a line width/line spacing of a redistribution layer of the circuit structure conforms with a line width/line spacing of the electronic element. Therefore, when the size specification of the electronic element is designed to be miniaturized, the redistribution layer configured in the circuit structure can effectively match the line spacing/line width of the electronic element, so as to meet the requirements of miniaturized packaging.Type: ApplicationFiled: April 21, 2022Publication date: August 17, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Feng Kao, Lung-Yuan Wang
-
Publication number: 20230178451Abstract: A method of manufacturing an electronic package is provided, in which a package module including a routing structure is stacked on a carrier structure via a plurality of conductive elements, a heat dissipation member covers a part of a surface of the routing structure, and an electronic module is disposed on another part of the surface of the routing structure, so that the routing structure is formed with at least one heat dissipation pad bonded to the heat dissipation member, such that the heat energy of the electronic module and the package module can be dissipated via the heat dissipation pad and the heat dissipation member.Type: ApplicationFiled: September 14, 2022Publication date: June 8, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Hsin-Jou Lin, Lung-Yuan Wang, Feng Kao, Chiu-Ling Chen
-
Publication number: 20220304157Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.Type: ApplicationFiled: June 2, 2022Publication date: September 22, 2022Inventors: Lung-Yuan WANG, Wen-Liang Lien
-
Patent number: 11382214Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.Type: GrantFiled: October 1, 2019Date of Patent: July 5, 2022Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lung-Yuan Wang, Wen-Liang Lien
-
Publication number: 20220068867Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.Type: ApplicationFiled: November 24, 2020Publication date: March 3, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Feng Kao, Lung-Yuan Wang
-
Publication number: 20220068801Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.Type: ApplicationFiled: November 23, 2020Publication date: March 3, 2022Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Feng Kao, Lung-Yuan Wang
-
Publication number: 20220005786Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
-
Patent number: 11152331Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: GrantFiled: November 4, 2019Date of Patent: October 19, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
-
Publication number: 20210051800Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.Type: ApplicationFiled: October 1, 2019Publication date: February 18, 2021Inventors: Lung-Yuan Wang, Wen-Liang Lien
-
Publication number: 20200388591Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: ApplicationFiled: November 4, 2019Publication date: December 10, 2020Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
-
Patent number: 10236261Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.Type: GrantFiled: April 20, 2017Date of Patent: March 19, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Fang-Lin Tsai, Yi-Feng Chang, Lung-Yuan Wang
-
Patent number: 10163662Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.Type: GrantFiled: April 4, 2017Date of Patent: December 25, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
-
Publication number: 20180211925Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.Type: ApplicationFiled: April 20, 2017Publication date: July 26, 2018Inventors: Fang-Lin Tsai, Yi-Feng Chang, Lung-Yuan Wang
-
Publication number: 20180138158Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Shu-Huei Huang
-
Patent number: 9905546Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.Type: GrantFiled: March 14, 2014Date of Patent: February 27, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Huei Huang
-
Publication number: 20170207104Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.Type: ApplicationFiled: April 4, 2017Publication date: July 20, 2017Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang