Patents by Inventor Lunkai Zhang

Lunkai Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404582
    Abstract: Technology is disclosed for controlling reads in a memory device supporting different types of reads having different performance times (e.g., a relatively fast read such as a globally-referenced read and a slower read such as a self-referenced read). The data out latencies of the different read types may be different to accommodate the different performance times. The memory controller may mix the different types of reads. The memory controller tracks expected usage of the data bus and schedules read commands accordingly to avoid data collisions. A countdown timer may be used to track the earliest clock cycle at which the memory device may return data for a new read command to be issued. The memory controller may record what clock cycles the data bus is projected to be occupied with data and schedule read commands based on the projected data bus occupancy to avoid data collisions.
    Type: Application
    Filed: July 27, 2023
    Publication date: December 5, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rasmus Madsen, Lunkai Zhang, Martin Lueker-Boden
  • Publication number: 20240386981
    Abstract: A bypass buffer stores codewords that have been identified as worn out codewords due to stuck-at-failure bit errors and/or other endurance failures. A controller of a data storage device monitors the number of worn out bits of a codeword stored by a memory device of the data storage device. If the number of worn out bits of the codeword exceeds a threshold number of worn out bits, data associated with the codeword is corrected and stored in the bypass buffer. The memory address associated with the codeword is also stored in the bypass buffer and associated with the corrected codeword.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 21, 2024
    Inventors: Lunkai Zhang, Nathan Franklin, Raj Ramanujan, Martin Lueker-Boden
  • Publication number: 20240361925
    Abstract: A data storage device has a controller, a decryption engine, and a memory storing encrypted data. Instead of using the decryption engine to generate a tweak value needed to decrypt the encrypted data, the tweak value is generated by the controller while the controller is waiting for the encrypted data to be read from the memory. This hides the latency to compute the tweak value in the latency to read the encrypted data from the memory.
    Type: Application
    Filed: July 19, 2023
    Publication date: October 31, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Mark Branstad, Martin Lueker-Boden, Lunkai Zhang
  • Publication number: 20240302964
    Abstract: A control circuit for a non-volatile memory array includes an interface to receive requests, a common request queue connected to the interface and a common request buffer connected to the common request queue. The common request buffer is configured to receive the requests from the common request queue in their received order and buffer unfinished requests directed to memory addresses such that for any address in the non-volatile memory array no more than one unfinished request is in the common request buffer.
    Type: Application
    Filed: July 27, 2023
    Publication date: September 12, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Lunkai Zhang, Rasmus Madsen, Martin Lueker-Boden
  • Publication number: 20220359030
    Abstract: Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 10, 2022
    Inventors: Yuanyuan Li, Rakan Maddah, Prashant S. Damle, Dany-Sebastien Ly-Gagnon, Lunkai Zhang
  • Publication number: 20210193248
    Abstract: A “near miss” based refresh scheme performs refreshes to read disturbed codewords proactively (or on-demand). In one example, a controller receives a read request to a target address (e.g., from a host memory controller). The read request is sent to memory, and the memory returns the read data. ECC logic decodes the read data and determines the number of error bits in the read data. If the number of error bits is greater than a threshold, a refresh write command is sent to the command queue. If an outstanding write command to the same address is already in the queue, the refresh write can be dropped and the outstanding write command converted into a refresh write command. A data cache can service read commands to the target address until the near miss-based refresh command completes.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 24, 2021
    Inventors: Lunkai ZHANG, Rakan MADDAH, Prashant S. DAMLE
  • Patent number: 10002023
    Abstract: A method and an apparatus for managing and scheduling tasks in a many-core system are presented. The method improves process management efficiency in the many-core system. The method includes, when a process needs to be added to a task linked list, adding a process descriptor pointer of the process to a task descriptor entry corresponding to the process, and adding the task descriptor entry to the task linked list; if a process needs to be deleted, finding a task descriptor entry corresponding to the process, and removing the task descriptor entry from the task linked list; and when a processor core needs to run a new task, removing an available priority index register with a highest priority from a queue of the priority index register.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 19, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lunkai Zhang, DongRui Fan, Hao Zhang, Xiaochun Ye
  • Publication number: 20160103709
    Abstract: A method and an apparatus for managing and scheduling tasks in a many-core system are presented. The method improves process management efficiency in the many-core system. The method includes, when a process needs to be added to a task linked list, adding a process descriptor pointer of the process to a task descriptor entry corresponding to the process, and adding the task descriptor entry to the task linked list; if a process needs to be deleted, finding a task descriptor entry corresponding to the process, and removing the task descriptor entry from the task linked list; and when a processor core needs to run a new task, removing an available priority index register with a highest priority from a queue of the priority index register.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 14, 2016
    Inventors: Lunkai Zhang, DongRui Fan, Hao Zhang, Xiaochun Ye