Patents by Inventor Lup San Leong
Lup San Leong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8828858Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.Type: GrantFiled: January 19, 2012Date of Patent: September 9, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
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Publication number: 20140117545Abstract: A copper layer is formed without copper hillocks. Embodiments includes providing a copper layer above a substrate, planarizing the copper layer, performing hydrogen (H2) plasma treatment on the copper layer in a first chamber, and forming a barrier layer over the copper layer in a second chamber, different from the first chamber.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. LtdInventors: Huang LIU, Xuesong Rao, Zheng Zou, Alex See, Lup San Leong, Liang Li, Chim Seng Seet
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Publication number: 20140008810Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: ApplicationFiled: July 5, 2012Publication date: January 9, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
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Publication number: 20130187202Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
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Patent number: 8492236Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.Type: GrantFiled: January 12, 2012Date of Patent: July 23, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
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Publication number: 20130181259Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
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Patent number: 7947604Abstract: The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.Type: GrantFiled: January 25, 2008Date of Patent: May 24, 2011Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Fan Zhang, Lup San Leong, Yong Kong Siew, Bei Chao Zhang
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Patent number: 7833900Abstract: The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.Type: GrantFiled: March 14, 2008Date of Patent: November 16, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Lup San Leong, Yong Kong Siew, Liang Choo Hsia
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Publication number: 20100206818Abstract: The present invention relates to semiconductor processing. In particular, it relates to a tunable ultrasonic filter and a method of using the same for more effective separation of large particles from slurry. In one embodiment a standing wave is produced in the filter and large particles are accumulated at the nodes of the standing waves while the slurry is flowed out of the filter.Type: ApplicationFiled: February 19, 2009Publication date: August 19, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Lup San Leong, Feng Zhao, Benfu Lin, Haigou Huang, Xianbin Wang
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Publication number: 20090233441Abstract: The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.Type: ApplicationFiled: March 14, 2008Publication date: September 17, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Lup San Leong, Yong Kong Siew, Liang Choo Hsia
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Publication number: 20090191792Abstract: The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.Type: ApplicationFiled: January 25, 2008Publication date: July 30, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Fan ZHANG, Lup San LEONG, Yong Kong SIEW, Bei Chao ZHANG
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Patent number: 7156726Abstract: In one embodiment, a dielectric layer (144, 156) overlying a semiconductor substrate (28) is uniformly polished. During polishing, the perimeter (32) of the semiconductor substrate (28) overlies a peripheral region (16, 48, 66, 86, 120) of a polishing pad (6, 42, 60, 80, 100) and an edge portion (36) of the front surface of semiconductor substrate (28) is not in contact with the front surface (18, 50, 68, 88, 122) of the polishing pad (6, 42, 60, 80, 100), in the peripheral region (16, 48, 66, 86, 120). As a result, the polishing rate at the edge portion (36) of the semiconductor substrate (28) is reduced, and the semiconductor substrate (28) is polished with improved center to edge uniformity. Since the semiconductor substrate (28) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion (36) of the semiconductor substrate (28) are not over polished.Type: GrantFiled: July 12, 2001Date of Patent: January 2, 2007Assignee: Chartered Semiconductor Manufacturing LimitedInventors: Feng Chen, Lup San Leong, Charles Lin
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Patent number: 6964598Abstract: In one embodiment, a semiconductor substrate (38) is uniformly polished using a polishing pad (16) that has a first polishing region (26), a second polishing region (28), and a third polishing region (30). The semiconductor substrate (38) is aligned to the polishing pad (16), such that the center of the semiconductor substrate (38) overlies the second polishing region (28), and the edge of the semiconductor substrate overlies the first polishing region (26) and the third polishing region (30). During polishing, the semiconductor substrate (38) is not radially oscillated over the surface of the polishing pad, and as a result a more uniform polishing rate is achieved across the semiconductor substrate (38). This allows the semiconductor substrate (38) to be uniformly polished from center to edge, and increases die yield because die located on the semiconductor substrate (38) are not over polished.Type: GrantFiled: July 12, 2001Date of Patent: November 15, 2005Assignee: Chartered Semiconductor Manufacturing LimitedInventors: Lup San Leong, Feng Chen, Charles Lin
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Publication number: 20040087098Abstract: An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing.Type: ApplicationFiled: November 1, 2002Publication date: May 6, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Chit Hwei Ng, Chaw Sing Ho, Lup San Leong, Shao Kai, Raymond Jacob Joy, Sanford Chu, Sajan Marokkey Raphael
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Patent number: 6730573Abstract: An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing.Type: GrantFiled: November 1, 2002Date of Patent: May 4, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chit Hwei Ng, Chaw Sing Ho, Lup San Leong, Shao Kai, Raymond Jacob Joy, Sanford Chu, Sajan Marokkey Raphael
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Publication number: 20020164875Abstract: A method and equipment is provided for planarization of ILD layers on a semiconductor wafer. The method includes providing an oven having a wafer holder therein, placing the semiconductor wafer on the wafer holder, and simultaneously applying mechanical pressure and heat to the ILD layer on the semiconductor wafer using a mechanical device.Type: ApplicationFiled: May 4, 2001Publication date: November 7, 2002Inventor: Lup San Leong
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Patent number: 6443809Abstract: In one embodiment, a semiconductor substrate (38) is uniformly polished using a polishing pad (16) that has a first polishing region (26), a second polishing region (28), and a third polishing region (30). The semiconductor substrate (38) is aligned to the polishing pad (16), such that the center of the semiconductor substrate (38) overlies the second polishing region (28), and the edge of the semiconductor substrate overlies the first polishing region (26) and the third polishing region (30). During polishing, the semiconductor substrate (38) is not radially oscillated over the surface of the polishing pad, and as a result a more uniform polishing rate is achieved across the semiconductor substrate (38). This allows the semiconductor substrate (38) to be uniformly polished from center to edge, and increases die yield because die located on the semiconductor substrate (38) are not over polished.Type: GrantFiled: November 16, 1999Date of Patent: September 3, 2002Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Lup San Leong, Feng Chen, Charles Lin
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Patent number: 6376378Abstract: In one embodiment, a dielectric layer (144, 156) overlying a semiconductor substrate (28) is uniformly polished. During polishing, the perimeter (32) of the semiconductor substrate (28) overlies a peripheral region (16, 48, 66, 86, 120) of a polishing pad (6, 42, 60, 80, 100) and an edge portion (36) of the front surface of semiconductor substrate (28) is not in contact with the front surface (18, 50, 68, 88, 122) of the polishing pad (6, 42, 60, 80, 100), in the peripheral region (16, 48, 66, 86, 120). As a result, the polishing rate at the edge portion (36) of the semiconductor substrate (28) is reduced, and the semiconductor substrate (28) is polished with improved center to edge uniformity. Since the semiconductor substrate (28) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion (36) of the semiconductor substrate (28) are not over polished.Type: GrantFiled: October 8, 1999Date of Patent: April 23, 2002Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Feng Chen, Lup San Leong, Charles Lin