Abstract: In accordance with an aspect of the present invention, an external FET driving circuit includes a driving portion, a drain-to-gate clamp portion and a current feedback portion. The driving portion provides a driving signal to the external FET. The drain-to-gate clamp portion protects the external FET from flyback current, when the external FET is quickly turned OFF. The current feedback portion controls the driving signal provided by the driver.

Abstract: In accordance with an aspect of the present invention, an external FET driving circuit includes a driving portion, a drain-to-gate clamp portion and a current feedback portion. The driving portion provides a driving signal to the external FET. The drain-to-gate clamp portion protects the external FET from flyback current, when the external FET is quickly turned OFF. The current feedback portion controls the driving signal provided by the driver.

Abstract: The cascoded gain single stage amplifier includes: a common gate differential pair; a first amplifier having a first input coupled to a first leg of the differential pair, and a second input coupled to a second leg of the differential pair; a current mirror coupled to the differential pair; a second amplifier having a first input coupled to a first leg of the current mirror, and a second input coupled to a second leg of the current mirror.

Abstract: The voltage matching circuit includes: a first branch including a first transistor; a second branch including a second transistor; and a cascaded level shifter coupled between the first and second branches to match a voltage on the first transistor with a voltage on the second transistor.

Abstract: The present invention provides a system for producing high voltage, low power driver circuitry (300) that addresses a number of disparate design requirements. The present invention provides circuitry comprising a voltage supply (308) and an output node (302). A transistor (304) is provided. A first resistive element (312) is coupled to the voltage supply, while a second resistive element (314)—having a resistance value equal to that of the first resistive element—is coupled between a second terminal of the transistor and the output node. A first diode (310) is coupled to the first resistive element and to a first terminal of the transistor. A clamping system (316) is coupled to the transistor, and a current limiting system (318) is coupled to the clamping system.

Abstract: A current monitor (360) having a high performance, simple, and cost effective design that is independent of process, temperature and voltage is disclosed herein. The current monitor (360) includes a sensing transistor (340) that couples to the main transistor (312) of an adjoining voltage regulator. Specifically, the control and source nodes of each transistor couple to each other, respectively. The size of the main transistor (312) is a predetermined multiple integer n of the size of the sensing transistor. A first resistor (RS3) couples between a supply voltage and the drain node of the main transistor (312). A second resistor (RS1) couples between a supply voltage and the drain node of the sensing transistor (340), wherein the size of the second resistor (RS1) is equal to the size of the first resistor (RS3) multiplied by the predetermined multiple integer n.