Patents by Inventor Luting Ye

Luting Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital resolver decoder with hardware filter and rectifier
    Patent number: 11567471
    Abstract: A resolver decoder circuit includes: a first filter circuit configured to calculate a first weighted sum of a first digital signal over a pre-determined period of time, where the first digital signal includes first digital samples of a first analog signal from a sine winding of a resolver; a second filter circuit configured to calculate a second weighted sum of a second digital signal over the pre-determined period of time, where the second digital signal includes second digital samples of a second analog signal from a cosine winding of the resolver, where the first and the second analog signals are configured to be induced by a sine signal applied to an input winding of the resolver; and a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: January 31, 2023
    Assignee: STMicroelectronics (China) Investment Co.
    Inventors: Jian Wang, Luting Ye, Xiaobo Sun
  • DIGITAL RESOLVER DECODER WITH HARDWARE FILTER AND RECTIFIER
    Publication number: 20220413462
    Abstract: A resolver decoder circuit includes: a first filter circuit configured to calculate a first weighted sum of a first digital signal over a pre-determined period of time, where the first digital signal includes first digital samples of a first analog signal from a sine winding of a resolver; a second filter circuit configured to calculate a second weighted sum of a second digital signal over the pre-determined period of time, where the second digital signal includes second digital samples of a second analog signal from a cosine winding of the resolver, where the first and the second analog signals are configured to be induced by a sine signal applied to an input winding of the resolver; and a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 29, 2022
    Inventors: Jian Wang, Luting Ye, Xiaobo Sun