Abstract: In certain embodiments, a circuit comprises a first voltage source configured to provide a supply voltage at an output of the first voltage source for a subcircuit. The circuit further comprises at least one second voltage source configured to provide output voltage to supply the subcircuit when the first voltage source is deactivated. The circuit further comprises an evaluation circuit connectable to an output of the at least one second voltage source, to a control input of the at least one second voltage source, and to the output of the first voltage source. The evaluation circuit is configured to adjust, based on the supply voltage at the output of the first voltage source, an output voltage of the at least one second voltage source.

Abstract: An example circuit includes a voltage regulator, a controller, and a chain of switches. The voltage regulator is configured to generate a supply voltage, the supply voltage connected to each switch in the chain of switches, and generate a supply voltage status signal, the supply voltage status signal indicating a status of the supply voltage. The chain of switches includes a first switch configured to switch the supply voltage to a first subcircuit of a plurality of sub circuits based on the supply voltage status signal and one or more second switches configured to switch the supply voltage to one or more respective subcircuits of the plurality of subcircuits.

Abstract: A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values.

Abstract: A circuit, use, and method for operating a circuit is provided that includes a regulated first voltage source for providing a supply voltage at an output of the first voltage source for a subcircuit, an adjustable second voltage source for providing an output voltage to supply the subcircuit, and an evaluation circuit, which is connected to an output of the second voltage source and to a control input of the second voltage source and to the output of the first voltage source. Wherein the evaluation circuit is formed to adjust the output voltage of the second voltage source by means of a control signal at the control input of the second voltage source with evaluation of the supply voltage at the output of the first voltage source, and wherein the evaluation circuit and/or the second voltage source have a memory for storing values of the adjustment.

Abstract: A circuit, use, and method for operating a circuit is provided that includes a regulated first voltage source for providing a supply voltage at an output of the first voltage source for a subcircuit, an adjustable second voltage source for providing an output voltage to supply the subcircuit, and an evaluation circuit, which is connected to an output of the second voltage source and to a control input of the second voltage source and to the output of the first voltage source. Wherein the evaluation circuit is formed to adjust the output voltage of the second voltage source by means of a control signal at the control input of the second voltage source with evaluation of the supply voltage at the output of the first voltage source, and wherein the evaluation circuit and/or the second voltage source have a memory for storing values of the adjustment.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: A monolithic integrated circuit is provided that includes a semiconductor switch, a constant current source, a capacitor, and a load circuit, which has a load capacitance. An output of the semiconductor switch is connected to the load circuit to turn on and off a supply voltage of the load circuit. The capacitor is connected to the output of the semiconductor switch and to a control input of the semiconductor switch. The constant current source can be or is connected to the control input of the semiconductor switch. Also, a use of a semiconductor switch is provided to reduce the leakage current of a load circuit of a monolithic integrated circuit.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Abstract: A circuit, control method, and use of a circuit for a sleep mode and an operating mode with a digital CMOS circuit with NMOS field-effect transistors and with PMOS field-effect transistors, with a first load device, whereby source terminals of the NMOS field-effect transistors of the digital CMOS circuit are connected via the first load device to a first supply voltage, and with a second load device, whereby source terminals of the PMOS field-effect transistors of the digital CMOS circuit are connected via the second load device to a second supply voltage, wherein the body terminals of the NMOS field-effect transistors of the digital CMOS circuit are connected directly to the first supply voltage, and the body terminals of the PMOS field-effect transistors of the digital CMOS circuit are connected directly to the second supply voltage.

Abstract: A circuit, use, and method for operating a circuit is provided that includes a regulated first voltage source for providing a supply voltage at an output of the first voltage source for a subcircuit, an adjustable second voltage source for providing an output voltage to supply the subcircuit, and an evaluation circuit, which is connected to an output of the second voltage source and to a control input of the second voltage source and to the output of the first voltage source. Wherein the evaluation circuit is formed to adjust the output voltage of the second voltage source by means of a control signal at the control input of the second voltage source with evaluation of the supply voltage at the output of the first voltage source, and wherein the evaluation circuit and/or the second voltage source have a memory for storing values of the adjustment.

Abstract: A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values.

Abstract: A monolithic integrated circuit is provided that includes a semiconductor switch, a constant current source, a capacitor, and a load circuit, which has a load capacitance. An output of the semiconductor switch is connected to the load circuit to turn on and off a supply voltage of the load circuit. The capacitor is connected to the output of the semiconductor switch and to a control input of the semiconductor switch. The constant current source can be or is connected to the control input of the semiconductor switch. Also, a use of a semiconductor switch is provided to reduce the leakage current of a load circuit of a monolithic integrated circuit.

Abstract: An automatic power level control circuit provides output power control of a transmitter device as used in wireless LAN applications in that an output signal is detected and a corresponding control voltage of a DAC in the base band section is corresponding adjusted. Preferably, the measurement of the output power is carried out during a first transmit cycle and the DAC is adjusted after completion of the first transmit cycle and prior to the begin of a subsequent transmit cycle. Thus, a reliable output level control is obtained with a minimum number of radio frequency components, wherein the control loop shows an enhanced stability due to the time-discrete control operation.