Patents by Inventor Lutz Goergens
Lutz Goergens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8946767Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.Type: GrantFiled: June 4, 2012Date of Patent: February 3, 2015Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Sonja Krumrey
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Patent number: 8907340Abstract: A semiconductor arrangement includes a semiconductor body and a semiconductor device, the semiconductor device including first and second load terminals arranged distant to each other in a first direction of the semiconductor body and a load path arranged in the semiconductor body between the first and second load terminals. The semiconductor arrangement further includes at least one Hall sensor arranged in the semiconductor body distant to the semiconductor device in a second direction perpendicular to the first direction. The Hall sensor includes two current supply terminals and two measurement terminals.Type: GrantFiled: September 23, 2011Date of Patent: December 9, 2014Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Walter Rieger, Lutz Goergens, Helmut Angerer, Gianmauro Pozzovivo, Markus Zundel
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Patent number: 8853776Abstract: An electronic circuit includes a transistor device that can be operated in a reverse operation mode and a control circuit. The transistor device includes a source region, a drain region, a body region and a drift region, a source electrode electrically connected to the source region, a pn junction formed between the body region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region, and a depletion control structure adjacent the drift region. The depletion control structure has a control terminal and is configured to generate a depletion region in the drift region dependent on a drive signal received at the control terminal. The control circuit is coupled to the control terminal of the depletion control structure and configured to drive the depletion control structure to generate the depletion region when the transistor device is operated in the reverse operation mode.Type: GrantFiled: September 21, 2011Date of Patent: October 7, 2014Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Lutz Goergens, Martin Feldtkeller
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Publication number: 20130140673Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.Type: ApplicationFiled: June 4, 2012Publication date: June 6, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey
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Publication number: 20130075724Abstract: A semiconductor arrangement includes a semiconductor body and a semiconductor device, the semiconductor device including first and second load terminals arranged distant to each other in a first direction of the semiconductor body and a load path arranged in the semiconductor body between the first and second load terminals. The semiconductor arrangement further includes at least one Hall sensor arranged in the semiconductor body distant to the semiconductor device in a second direction perpendicular to the first direction. The Hall sensor includes two current supply terminals and two measurement terminals.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Walter Rieger, Lutz Goergens, Helmut Angerer, Gianmauro Pozzovivo, Markus Zundel
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Publication number: 20130069710Abstract: An electronic circuit includes a transistor device that can be operated in a reverse operation mode and a control circuit. The transistor device includes a source region, a drain region, a body region and a drift region, a source electrode electrically connected to the source region, a pn junction formed between the body region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region, and a depletion control structure adjacent the drift region. The depletion control structure has a control terminal and is configured to generate a depletion region in the drift region dependent on a drive signal received at the control terminal. The control circuit is coupled to the control terminal of the depletion control structure and configured to drive the depletion control structure to generate the depletion region when the transistor device is operated in the reverse operation mode.Type: ApplicationFiled: September 21, 2011Publication date: March 21, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Lutz Goergens, Martin Feldtkeller
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Patent number: 8193559Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.Type: GrantFiled: April 7, 2011Date of Patent: June 5, 2012Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey, Sonja Krumrey, legal representative
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Patent number: 8120161Abstract: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.Type: GrantFiled: April 10, 2007Date of Patent: February 21, 2012Assignee: Infineon Technologies AGInventors: Ralf Otremba, Lutz Goergens, Gerhard Noebauer, Tien Lai Tan, Erwin Huber, Marco Puerschel, Gilles Delarozee, Markus Dinkel
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Publication number: 20110241170Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.Type: ApplicationFiled: April 7, 2011Publication date: October 6, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey, Sonja Krumrey
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Patent number: 8031498Abstract: An active diode is disclosed. One embodiment provides a method for operating a device. The electronic device includes a transistor connected between a first and a second connection of the electronic device; a control device coupled to a control connection of the transistor; and an energy storage device coupled to the control device.Type: GrantFiled: July 5, 2007Date of Patent: October 4, 2011Assignee: Infineon Technologies Austria AGInventors: Gerald Deboy, Lutz Goergens
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Patent number: 7943955Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.Type: GrantFiled: January 27, 2009Date of Patent: May 17, 2011Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Lutz Goergens, Martin Poelzl, Johannes Schoiswohl, Joachim Krumrey
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Publication number: 20100187605Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.Type: ApplicationFiled: January 27, 2009Publication date: July 29, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Lutz Goergens, Martin Poelzl, Johannes Schoiswohl, Joachim Krumrey
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Publication number: 20090086512Abstract: An apparatus, comprising a transformer comprising a first winding and a second winding; a first switch coupled to the first winding and configured to alternate between an off state and an on state in response to a pulsed first signal; a rectifier coupled to the second winding and configured to alternate between an off state and an on state in response to a pulsed second signal; and a drive circuit configured to generate the first and second signals such that the first switch and the rectifier are switched to the on state in a temporally offset relation with each other.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Marc Fahlenkamp, Harald Zoellinger, Gerald Deboy, Lutz Goergens
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Publication number: 20090010033Abstract: An active diode is disclosed. One embodiment provides a method for operating a device. The electronic device includes a transistor connected between a first and a second connection of the electronic device; a control device coupled to a control connection of the transistor; and an energy storage device coupled to the control device.Type: ApplicationFiled: July 5, 2007Publication date: January 8, 2009Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Gerald Deboy, Lutz Goergens
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Publication number: 20080251859Abstract: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Inventors: Ralf Otremba, Lutz Goergens, Gerhard Noebauer, Charlie Tan Tien Lai, Erwin Huber, Marco Puerschel, Gilles Delarozee, Markus Dinkel