Patents by Inventor Lutz Herrmann

Lutz Herrmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8114650
    Abstract: A method for producing a ciliate cell with reduced or essentially no dihydrofolate reductase (DHFS) activity or reduced or essentially no thymidylate synthase (TS) activity or both reduced or essentially no dihydrofolate reductase and thymidylate synthase (DHFR-TS) activity is claimed, comprising the steps of a) transforming ciliate cells by inserting a construct containing an allele altering the gene encoding the endogenous DHFR-TS into at least one of the endogenous DHFR-TS genes of the ciliate macronucleus (MAC), b) inducing an allelic assortment process in the transformed ciliate cells to generate cells having the construct inserted in most or all functional DHFR-TS genes of the MAC, and c) identifying the cells generated in step b) by cultivation with or without thymidine.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: February 14, 2012
    Assignee: Cilian AG
    Inventors: Thomas Weide, Ulrike Bockau, Marcus Hartmann, Lutz Herrmann
  • Patent number: 7723506
    Abstract: A method characterizes samples having units by monitoring fluctuating intensities of radiation emitted, scattered, and/or reflected by the units in at least one measurement volume, the monitoring being performed by at least one detection device, the method comprising the steps of: a) measuring in a repetitive mode a number of photon counts per time interval of defined length, b) determining a function of the number of photon counts per the time interval, and c) determining a function of specific brightness of the units on basis of the function of the number of photon counts.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: May 25, 2010
    Assignee: Cilian AG
    Inventors: Marcus Hartmann, Thomas Weide, Lutz Herrmann, Nadine Niebur
  • Publication number: 20100021952
    Abstract: A method for producing a ciliate cell with reduced or essentially no dihydrofolate reductase (DHFS) activity or reduced or essentially no thymidylate synthase (TS) activity or both reduced or essentially no dihydrofolate reductase and thymidylate synthase (DHFR-TS) activity is claimed, comprising the steps of a) transforming ciliate cells by inserting a construct containing an allele altering the gene encoding the endogenous DHFR-TS into at least one of the endogenous DHFR-TS genes of the ciliate macronucleus (MAC), b) inducing an allelic assortment process in the transformed ciliate cells to generate cells having the construct inserted in most or all functional DHFR-TS genes of the MAC, and c) identifying the cells generated in step b) by cultivation with or without thymidine.
    Type: Application
    Filed: September 20, 2006
    Publication date: January 28, 2010
    Inventors: Thomas Weide, Ulrike Bockau, Marcus Hartmann, Lutz Herrmann
  • Publication number: 20080261290
    Abstract: The present invention relates to heat-inducible promoters of the heat shock protein family of the ciliate Tetrahymena thermophila, especially a promoter having the nucleotide sequence of Seq. ID No. 1 or promoter-effective fragments thereof. Furthermore the use of heat-inducible promoters of the present invention for the expression of homologous and/or heterologous proteins in the ciliate Tetrahymena thermophila is claimed.
    Type: Application
    Filed: July 13, 2006
    Publication date: October 23, 2008
    Inventors: Marcus Hartmann, Thomas Weide, Lutz Herrmann, Nadine Niebur
  • Patent number: 7299105
    Abstract: Methods and systems are disclosed that allow an adjustment of a product parameter, such as operating speed, of a circuit element, such as a field effect transistor, during the fabrication of the device. A manufacturing process downstream of a first controlled process is controlled by a superior control scheme in response to the measurement data of the first and second processes and on the basis of a sensitivity function, which describes the effect a variation of the product parameter generates in the measurement data. The superior control scheme may provide a compensated target value for the downstream process.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: November 20, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andre Holfeld, Jan Raebiger, Lutz Herrmann
  • Publication number: 20050192700
    Abstract: Methods and systems are disclosed that allow an adjustment of a product parameter, such as operating speed, of a circuit element, such as a field effect transistor, during the fabrication of the device. A manufacturing process downstream of a first controlled process is controlled by a superior control scheme in response to the measurement data of the first and second processes and on the basis of a sensitivity function, which describes the effect a variation of the product parameter generates in the measurement data. The superior control scheme may provide a compensated target value for the downstream process.
    Type: Application
    Filed: January 6, 2005
    Publication date: September 1, 2005
    Inventors: Andre Holfeld, Jan Raebiger, Lutz Herrmann
  • Patent number: 6812159
    Abstract: A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Patent number: 6808970
    Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: October 26, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Feudel, Christian Krueger, Lutz Herrmann
  • Publication number: 20040192057
    Abstract: The present invention provides a technique for forming extremely thin insulation layers requiring the incorporation of specified amounts of nitrogen, wherein the effect of nitrogen variations across the substrate surface may be reduced in that during and/or after the nitrogen incorporation an oxidation process is performed. The nitrogen variations lead to a nitrogen concentration dependent oxidation rate and, hence, a nitrogen concentration dependent thickness variation of the insulating layer. In particular, the threshold variations of transistors including the thin insulating layer as a gate insulation layer may effectively be reduced.
    Type: Application
    Filed: October 24, 2003
    Publication date: September 30, 2004
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Publication number: 20040126998
    Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.
    Type: Application
    Filed: June 24, 2003
    Publication date: July 1, 2004
    Inventors: Thomas Feudel, Christian Krueger, Lutz Herrmann
  • Patent number: 6723663
    Abstract: For aggressively scaled field effect transistors, nitrogen is incorporated into a base oxide layer, wherein, at an initial phase of a plasma nitridation process, the nitrogen ion density is maintained at a value so that incorporation of nitrogen into the channel region is minimized. Subsequently, when the thickness of the base oxide layer has increased, due to residual oxygen in the plasma ambient, the nitrogen ion density is increased, thereby increasing the nitridation rate. Preferably, the nitrogen ion density is controlled by varying the pressure of the plasma ambient. Moreover, a system is disclosed that allows control of the nitridation rate in response to an oxide layer thickness.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: April 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Publication number: 20040043627
    Abstract: A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.
    Type: Application
    Filed: April 22, 2003
    Publication date: March 4, 2004
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Patent number: D520374
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: May 9, 2006
    Assignee: The Procter & Gamble Company
    Inventors: Lutz Herrmann, Maike De Wall
  • Patent number: D417624
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: December 14, 1999
    Assignee: The Procter & Gamble Company
    Inventors: Lutz Herrmann, Veit Mahlmann
  • Patent number: D420595
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: February 15, 2000
    Assignee: The Procter & Gamble Company
    Inventor: Lutz Herrmann
  • Patent number: D421384
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: March 7, 2000
    Assignee: The Procter & Gamble Company
    Inventor: Lutz Herrmann
  • Patent number: D421572
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: March 14, 2000
    Assignee: The Procter & Gamble Company
    Inventor: Lutz Herrmann
  • Patent number: D422916
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: April 18, 2000
    Assignee: The Procter & Gamble Company
    Inventor: Lutz Herrmann
  • Patent number: D428340
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: July 18, 2000
    Assignee: The Procter & Gamble Company
    Inventor: Lutz Herrmann
  • Patent number: D430491
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: September 5, 2000
    Assignee: The Procter & Gamble Company
    Inventors: Lutz Herrmann, Veit Mahlmann