Patents by Inventor Lutz NAETHKE
Lutz NAETHKE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9558121Abstract: A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.Type: GrantFiled: December 28, 2012Date of Patent: January 31, 2017Assignee: INTEL CORPORATIONInventors: Li-Gao Zei, Fernando Latorre, Steffen Kosinski, Jaroslaw Topp, Varun Mohandru, Lutz Naethke
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Patent number: 9411724Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift.Type: GrantFiled: December 21, 2011Date of Patent: August 9, 2016Assignee: Intel CorporationInventors: Lutz Naethke, Eric Desmarais, Ralf Goettsche
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Patent number: 9195465Abstract: Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.Type: GrantFiled: December 28, 2012Date of Patent: November 24, 2015Assignee: Intel CorporationInventors: Varun K. Mohandru, Fernando Latorre, Li-Gao Zei, Allan D. Knies, Rami May, Lutz Naethke
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Patent number: 9189240Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.Type: GrantFiled: November 26, 2014Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Lutz Naethke, Axel Borkowski, Bert Bretschneider, Kyriakos A. Stavrou, Rainer Theuer
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Publication number: 20150081975Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.Type: ApplicationFiled: November 26, 2014Publication date: March 19, 2015Inventors: Lutz Naethke, Axel Borkowski, Bert Bretschneider, Kyriakos A. Stavrou, Rainer Theuer
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Patent number: 8924660Abstract: Method, process, and apparatus to efficiently store, read, and/or process portions of word data. A portion of a data word, which includes multiple portions, may be read by a computer processor. The processor may read a first portion of the data word from a first memory. The processor may read a second portion of the data word from a second portion of memory. The second portion may include bits which are less critical than the bits of the first portion. The second memory may be distinct from the first memory based on one or more physical attributes.Type: GrantFiled: March 21, 2014Date of Patent: December 30, 2014Assignee: Intel CorporationInventors: Lutz Naethke, Axel Borkowski, Bert Bretschneider, Kyriakos A. Stavrou, Rainer Theuer
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Publication number: 20140313520Abstract: The present disclosure relates to computer-implemented systems and methods for location determination using light sources. An example method may include receiving, by a computer including one or more processors, a location request for a device within an indoor environment. The method may also include receiving respective light source identifiers associated with one or more light sources in the indoor environment. The one or more light sources may be in communication with the device. Additionally, the method may include accessing, by the computer, a virtual map associated with the indoor environment, and the virtual map may include one or more associations between the respective light source identifiers and respective positions, within the indoor environment, of the one or more light sources. Furthermore, the method may include determining, based at least in part on the virtual map and the respective light source identifiers, a location of the device within the indoor environment.Type: ApplicationFiled: April 19, 2013Publication date: October 23, 2014Inventors: Lutz Naethke, Andrey Nikolaev, Avishay Sharaga, Zdravko Boos, Wing Yan Mok
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Publication number: 20140208033Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.Type: ApplicationFiled: March 21, 2014Publication date: July 24, 2014Inventors: Lutz Naethke, Axel Borkowski, Bert Bretschneider, Kyriakos A. Stavrou, Rainer Theuer
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Publication number: 20140189238Abstract: A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Li-Gao ZEI, Fernando LATORRE, Steffen KOSINSKI, Jaroslaw TOPP, Varun MOHANDRU, Lutz NAETHKE
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Publication number: 20140189253Abstract: Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Varun K. MOHANDRU, Fernando LATORRE, Li-Gao ZEI, Allan D. KNIES, Rami MAY, Lutz NAETHKE
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Patent number: 8719519Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.Type: GrantFiled: March 30, 2012Date of Patent: May 6, 2014Assignee: Intel CorporationInventors: Lutz Naethke, Axel Borkowski, Bert Bretschneider, Kyriakos A. Stavrou, Rainer Theuer
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Publication number: 20130339660Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift.Type: ApplicationFiled: December 21, 2011Publication date: December 19, 2013Inventors: Lutz Naethke, Eric Desmarais, Ralf Goettsche
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Publication number: 20130262793Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Applicant: INTEL CORPORATIONInventors: Lutz NAETHKE, Axel BORKOWSKI, Bert BRETSCHNEIDER, Kyriakos A. STAVROU, Rainer THEUER