Abstract: An example device includes splitter logic to split an input sample having a predetermined number of bits into a first segment of most significant bits and a second segment of least significant bits. Pulse logic generates a pattern of pulses that correlate to the values of the most significant bits. Edge mover logic determines edge adjustment data based on the values of the least significant bits, the edge adjustment data representing an adjustment to at least one edge in the pattern of pulses. Combiner logic generates an enhanced pulse stream by adjusting at least one edge in the pattern of pulses based on the edge adjustment data.

Abstract: An example device includes splitter logic to split an input sample having a predetermined number of bits into a first segment of most significant bits and a second segment of least significant bits. Pulse logic generates a pattern of pulses that correlate to the values of the most significant bits. Edge mover logic determines edge adjustment data based on the values of the least significant bits, the edge adjustment data representing an adjustment to at least one edge in the pattern of pulses. Combiner logic generates an enhanced pulse stream by adjusting at least one edge in the pattern of pulses based on the edge adjustment data.

Abstract: An example device includes splitter logic to split an input sample having a predetermined number of bits into a first segment of most significant bits and a second segment of least significant bits. Pulse logic generates a pattern of pulses that correlate to the values of the most significant bits. Edge mover logic determines edge adjustment data based on the values of the least significant bits, the edge adjustment data representing an adjustment to at least one edge in the pattern of pulses. Combiner logic generates an enhanced pulse stream by adjusting at least one edge in the pattern of pulses based on the edge adjustment data.

Abstract: An example device includes splitter logic to split an input sample having a predetermined number of bits into a first segment of most significant bits and a second segment of least significant bits. Pulse logic generates a pattern of pulses that correlate to the values of the most significant bits. Edge mover logic determines edge adjustment data based on the values of the least significant bits, the edge adjustment data representing an adjustment to at least one edge in the pattern of pulses. Combiner logic generates an enhanced pulse stream by adjusting at least one edge in the pattern of pulses based on the edge adjustment data.

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module.

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module.

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module.

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module.

Abstract: A system is provided which includes a signal generator for generating a periodic excitation signal and an analog to digital converter, wherein the system is configured to apply the periodic excitation signal to a network including a known first impedance and a second impedance and to take a first set of M digital samples of a first signal relating to the first impedance and a second set of M digital samples of a second signal relating to the second impedance with a sampling frequency that is an integer multiple of the frequency of the periodic signal. The system is further configured to determine the impedance value of the second impedance by calculating a relative phase difference between the first signal and the second signal using the first set of digital samples and the second set of digital samples.

Abstract: A system is provided which comprises a signal generator for generating a periodic excitation signal and an analog to digital converter, wherein the system is configured to apply the periodic excitation signal to a network comprising a known first impedance and a second impedance and to take a first set of M digital samples of a first signal relating to the first impedance and a second set of M digital samples of a second signal relating to the second impedance with a sampling frequency that is an integer multiple of the frequency of the periodic signal. The system is further configured to determine the impedance value of the second impedance by calculating a relative phase difference between the first signal and the second signal using the first set of digital samples and the second set of digital samples.