Abstract: An integrated circuit is provided that includes at least one first circuit component and at least one second circuit component, the first circuit component being connected via a level converter to the second circuit component. The level converter can be optionally activated or deactivated by the first circuit component in order to enable or prevent a data exchange between the first circuit component and the second circuit component.

Abstract: An automatic gain controller for transceiver elements uses a digital topology to achieve an efficient and rapid gain settling so that an output signal of the variable gain section is within a predefined range. In one embodiment, an input signal is periodically sampled and latched so as represent the gain excess of a variable gain section. An accumulator, including an adder having saturation characteristics and a latch as a feedback element, creates a number for a new gain setting so that the variable gain section may adapt to the new gain setting within one clock period. In one example, a gain range of 84 dB is controllable and settling is achieved within 3 clock periods at most.

Abstract: An electronic circuit with an improved current stabilization operating in an RF transceiver or receiver, e.g. in a wireless local area network system, and a corresponding method is provided for generating a supply current and supplying the generated supply current to at least two subunits of the electronic circuit. The at least two subunits are connected in parallel to each other. Each of the subunits receives an input voltage at an input transistor in the first one of at least two parallel current paths of the subunit. Each subunit stabilizes the current through the input transistor by means of a control circuit a second current path of the subunit and a common voltage output terminal is connected to each subunit for outputting a voltage. The provided technique may allow for detecting maximum values or generating absolute values.

Abstract: In a direct conversion radio frequency receiver, an automatic gain control is implemented that allows changing the operation mode of a filter unit in the baseband section of the receiver such that in a first operation mode filter capacities are selected to provide desired output signal characteristics, whereas in a second operation mode the filter settling time is significantly reduced in order to speed up gain adaptation and to improve gain loop stability. In one embodiment the cut-off frequency of a high pass filter and the Q-factor of a subsequent low pass filter are increased and decreased respectively upon changing the gain setting of a variable gain amplifier to accelerate settling of the filter.

Abstract: A radio frequency signal level is determined by generating an AC reference voltage from a DC reference voltage and determining an envelope of the AC reference voltage in an envelope detector having substantially the same composition as an envelope detector for determining the envelope of the radio frequency signal. The AC reference voltage substantially eliminates any DC offset and thus induces a high immunity against temperature and power supply variations. Moreover, using substantially the same RF signal path for the RF signal and the reference signal, signal distortions cause by the RF signal path are substantially compensated for.

Abstract: A tunable constant GM circuit allows to compensate for temperature and process variations with high precision by correspondingly adjusting a resistance value and/or the ratio of transistor widths. Thus, in switched capacitor circuits the frequency behaviour, such as the settling time, may be controlled by providing a compensated bias to the transconductance amplifiers typically used in these circuits.

Abstract: In one embodiment, an apparatus comprises a first integrated circuit and a second integrated circuit configured to be coupled to the first integrated circuit. The first integrated circuit comprises transceiver hardware configured to transmit and receive analog signals, one or more analog to digital converters coupled to the transceiver hardware, and one or more digital to analog converters coupled to the transceiver hardware. The analog to digital converters are configured to convert one or more received analog signals from the transceiver hardware to one or more received digital signals. The digital to analog converters are coupled to receive one or more transmitted digital signals, and are configured to convert the transmitted digital signals to transmitted analog signals for transmission by the transceiver hardware. The second integrated circuit comprises a baseband processor configured to process the received digital signals and to generate the transmitted digital signals.

Abstract: A receiver is provided for receiving a digitally modulated signal in a communication system. The receiver comprises a signal input unit adapted for determining at least one in-phase and at least one quadrature-phase value of the received signal. The receiver further comprises a signal generator connected to receive the in-phase and quadrature-phase values and to generate at least one modified in-phase value and at least one modified quadrature-phase value of a rotated phase constellation system. The receiver further comprises a signal processing unit that is adapted for processing the received signal dependent on the in-phase and quadrature-phase values and the modified in-phase and quadrature-phase values. The signal generator is a passive impedance network. Further, a corresponding integrated circuit chip and operation method are provided. Using a passive impedance network may simplify the hardware implementation by avoiding the need to provide an active amplifier.

Abstract: A FET square multiplier is disclosed that transforms an input signal into two currents I1 and I2, the difference of which is proportional to the square of the input signal. A first and a second FET are connected at their drains and are source-coupled to the source of a third FET whose transconductance is twice the transconductance of the first and the second FET. The common source node is biased by a constant current source. The FETs are operated in the saturation region to exploit the square dependency of the drain current on the difference of the gate-source voltage and the treshold voltage of an FET.

Abstract: An automatic power level control circuit provides output power control of a transmitter device as used in wireless LAN applications in that an output signal is detected and a corresponding control voltage of a DAC in the base band section is corresponding adjusted. Preferably, the measurement of the output power is carried out during a first transmit cycle and the DAC is adjusted after completion of the first transmit cycle and prior to the begin of a subsequent transmit cycle. Thus, a reliable output level control is obtained with a minimum number of radio frequency components, wherein the control loop shows an enhanced stability due to the time-discrete control operation.

Abstract: A radio frequency signal level is determined by generating an AC reference voltage from a DC reference voltage and determining an envelope of the AC reference voltage in an envelope detector having substantially the same composition as an envelope detector for determining the envelope of the radio frequency signal. The AC reference voltage substantially eliminates any DC offset and thus induces a high immunity against temperature and power supply variations. Moreover, using substantially the same RF signal path for the RF signal and the reference signal, signal distortions cause by the RF signal path are substantially compensated for.

Abstract: An electronic circuit with an improved current stabilization operating in an RF transceiver or receiver, e.g. in a wireless local area network system, and a corresponding method is provided for generating a supply current and supplying the generated supply current to at least two subunits of the electronic circuit. The at least two subunits are connected in parallel to each other. Each of the subunits receives an input voltage at an input transistor in the first one of at least two parallel current paths of the subunit. Each subunit stabilizes the current through the input transistor by means of a control circuit a second current path of the subunit and a common voltage output terminal is connected to each subunit for outputting a voltage. The provided technique may allow for detecting maximum values or generating absolute values.

Abstract: A technique for measuring peak voltages is provided that may be used in RF transceivers or receivers of wireless local area network systems. In an apparatus for measuring a peak value of an analog voltage, an analog to digital converter is connected to receive an input voltage. A voltage level detection unit detects a voltage level of a received input voltage, and a digital memory receives and stores the detected voltage level. The digital memory updates the stored voltage level only if the currently detected voltage level is higher, or lower, than the stored level. A digital code is output that corresponds to the stored voltage level. The provided technique may allow for a more simple and less complex implementation.

Abstract: A tunable constant GM circuit allows to compensate for temperature and process variations with high precision by correspondingly adjusting a resistance value and/or the ratio of transistor widths. Thus, in switched capacitor circuits the frequency behaviour, such as the settling time, may be controlled by providing a compensated bias to the transconductance amplifiers typically used in these circuits.

Abstract: A technique for measuring peak voltages is provided that may be used in RF transceivers or receivers of wireless local area network systems. An apparatus is provided for measuring a peak value of an analog voltage. The apparatus comprises an analog to digital converter that is connected to receive an input voltage. The analog to digital converter comprises a voltage level detection unit that detects a voltage level of the received input voltage, and a digital memory that is connected for receiving and storing the detected voltage level. The digital memory is adapted for updating the stored voltage level only if the currently detected voltage level is higher, or lower, than the stored level. A digital code is output that corresponds to the stored voltage level. The provided technique may allow for a more simple and less complex implementation.

Abstract: A receiver is provided for receiving a digitally modulated signal in a communication system. The receiver comprises a signal input unit adapted for determining at least one in-phase and at least one quadrature-phase value of the received signal. The receiver further comprises a signal generator connected to receive the in-phase and quadrature-phase values and to generate at least one modified in-phase value and at least one modified quadrature-phase value of a rotated phase constellation system. The receiver further comprises a signal processing unit that is adapted for processing the received signal dependent on the in-phase and quadrature-phase values and the modified in-phase and quadrature-phase values. The signal generator is a passive impedance network. Further, a corresponding integrated circuit chip and operation method are provided. Using a passive impedance network may simplify the hardware implementation by avoiding the need to provide an active amplifier.

Abstract: A receiver, an integrated circuit chip and a method are provided for estimating the power of a digitally modulated signal received by the receiver in a communication system. The method comprises determining in-phase and quadrature-phase values of a phase constellation system relating to the received signal, calculating at least one modified in-phase value and at least one modified quadrature-phase value relating to the phase constellation system rotated by a predetermined angle, and determining absolute values of the in-phase and quadrature-phase values and the modified in-phase and quadrature-phase values. The method further comprises identifying the maximum of the absolute values, and determining a power estimate of the received signal based on the identified maximum value. The provided technique may allow for estimating the power of a digitally modulated signal in a simple and less complex implementation.

Abstract: In the field of radio communication technology a WLAN (wireless local area network) receiver that has an AGC (automatic gain control unit) is provided, and a corresponding method of operating a WLAN receiver. In order to provide an improved WLAN receiver with a more efficient AGC unit having a reduced settling speed and a higher accuracy, a WLAN receiver is provided that comprises at least one controllable amplifier for receiving an input signal and generating an amplified input signal. The WLAN receiver further comprises an AGC controller for evaluating a signal strength of the amplified input signal and generating a control signal for controlling the gain of the controllable amplifier dependent thereon. The AGC controller is further arranged for evaluating a signal strength of the input signal and generating the control signal dependent on the signal strength of said input signal.

Abstract: An automatic gain controller for transceiver elements uses a digital topology to achieve an efficient and rapid gain settling so that an output signal of the variable gain section is within a predefined range. In one embodiment, an input signal is periodically sampled and latched so as represent the gain excess of a variable gain section. An accumulator, including an adder having saturation characteristics and a latch as a feedback element, creates a number for a new gain setting so that the variable gain section may adapt to the new gain setting within one clock period. In one example, a gain range of 84 dB is controllable and settling is achieved within 3 clock periods at most.

Abstract: In a direct conversion radio frequency receiver, an automatic gain control is implemented that allows changing the operation mode of a filter unit in the baseband section of the receiver such that in a first operation mode filter capacities are selected to provide desired output signal characteristics, whereas in a second operation mode the filter settling time is significantly reduced in order to speed up gain adaptation and to improve gain loop stability. In one embodiment the cut-off frequency of a high pass filter and the Q-factor of a subsequent low pass filter are increased and decreased respectively upon changing the gain setting of a variable gain amplifier to accelerate settling of the filter.