Abstract: A receiver includes an I-Q demodulator (135) responsive to the I and Q components carried on a first frequency signal line (132). A demodulator frequency generator (275) generates a demodulating signal to extract the carried I and Q components. A phase adjustment circuit (105) makes the demodulating signal substantially in phase with the first frequency signal. A transition detector (445) generates a state transition signal in response to a change of state of at least one of the I and Q signals. A peak detector (460) generates a peak detected signal in response to occurrence of a peak amplitude of at least one of the I and Q signals. A clock generator (470) adjusts the phase of a symbol clock signal used to decode the I and Q components in response to the state transition signal and peak detected signal.

Abstract: A receiver includes an I-Q demodulator (135) responsive to the I and Q components carried on a first frequency signal line (132). [The demodulator comprises a] A demodulator frequency generator (275) [for generating] generates a demodulating signal to extract the carried I and Q components. A phase adjustment circuit (105) [, responsive to the I and Q components that are maintained at a predetermined relationship,] makes the demodulating signal substantially in phase with the first frequency signal. A transition detector (445) generates a state transition signal in response to a change of state of at least one of the I and Q signals. A peak detector (460) generates a peak detected signal in response to occurrence of a peak amplitude of at least one of the I and Q signals. A clock generator (470) adjusts the phase of a symbol clock signal used to decode the I and Q components in response to the state transition signal and peak detected signal.

Abstract: A receiver includes an I-Q demodulator (135) responsive the I and Q components carried on a first frequency signal line (132). The demodulator comprises a demodulator frequency generator (275) for generating a demodulating signal to extract the carried I and Q components. A phase adjustment circuit (105), responsive to the I and Q components that are maintained at a predetermined relationship, makes the demodulating signal substantially in phase with the first frequency signal. A transition detector (445) generates a state transition signal in response to a change of state of at least one of the I and Q signals. A peak detector (460) generates a peak detected signal in response to occurrence of a peak amplitude of at least one of the I and Q signals. A clock generator (470) adjusts the phase of a symbol clock signal used to decode the I and Q components in response to the state transition signal and peak detected-signal.