Abstract: In an analog-to-digital converter (ADC) having storage capacitors, active, top-plate, n-type, switch circuitry has an n-type transistor and gate-voltage control circuitry that generates the gate voltage to turn on and off the transistor. The control circuitry turns off the transistor by generating the gate voltage at a level that limits the gate-to-source voltage difference, thereby limiting GISL leakage current through the transistor that can otherwise jeopardize the accuracy of the ADC digital output value. In one implementation, when the transistor is to be off (for example, during the ADC conversion phase), the control circuitry generates the gate voltage to be at ground if the source voltage is below a reference voltage, and above ground if the source voltage is above the reference voltage. The switch circuitry can also be implemented using a p-type device or a transmission gate instead of the n-type device.

Abstract: In an analog-to-digital converter (ADC) having storage capacitors, passive top-plate switch circuitry has at least one diode-configured transistor connected between a first transistor and the top-plate node of the storage capacitors to provide a diode-voltage drop that ensures that the voltage at the node between two transistors is different from the top-plate node voltage in order to reduce GIDL/GISL leakage current through the first transistor that could adversely affect the ADC's digital output value. A corresponding capacitor is connected across each diode-configured device to reduce the amount of charge needed to achieve intermediate-node, steady-state voltages when the switch circuitry is off. In an n-type implementation, a reverse-diode-biased isolation device is connected between the top-plate node and the at least one diode-configured device to prevent the top-plate node from seeing the large dynamic junction capacitance of the at least one diode-configured device.

Abstract: A level shifter includes a latch having first and second branches, first and second outputs, first and second control switches in series between the respective branches and outputs, and a controller receiving first and second output signals and outputting first and second control signals to the first and second control switches for controlling activation thereof. In an initial state, the first output signal is in the first state, the first control switch is activated, the second output signal is in the second state, and the second control switch is deactivated. In a final state, the first output signal is in the second state, the first control switch is deactivated, the second output signal is in the first state, and the second control switch is activated. The controller changes the first and second control signals only after the first and second output signals reach the respective second and first states.

Abstract: A level shifter includes a latch having first and second branches, first and second outputs, first and second control switches in series between the respective branches and outputs, and a controller receiving first and second output signals and outputting first and second control signals to the first and second control switches for controlling activation thereof. In an initial state, the first output signal is in the first state, the first control switch is activated, the second output signal is in the second state, and the second control switch is deactivated. In a final state, the first output signal is in the second state, the first control switch is deactivated, the second output signal is in the first state, and the second control switch is activated. The controller changes the first and second control signals only after the first and second output signals reach the respective second and first states.