Abstract: An apparatus includes a substrate including a planar surface. A die is attached to the planar surface of the substrate with an interposed die attach material. A solder mask is interposed between the die attach material and the planar surface. The solder mask includes a recessed portion extending beneath a periphery of the die, and the recessed portion is filled with a molding underfill.

Abstract: A substrate having a die attach area for receiving a semiconductor die includes a recessed area for receiving die attach adhesive. The recessed area prevents die attach adhesive from bleeding into the surrounding area and onto substrate connection sites, where it could compromise a wire bond formed on such a connection site. The recessed area has a zig-zag pattern, which allows for sufficient amounts of adhesive to be used to securely attach the die to the substrate, yet does not enlarge the recessed area such that the package size may be adversely affected.

Abstract: A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.

Abstract: A packaged IC device has a power bar assembly with one or more power distribution bars, mounted on top of the IC die, which enables assembly using a lead frame that does not include any power distribution bars. External power supply voltages are brought to the IC die by (i) a corresponding first bond wire that connects a lead frame lead to a corresponding die-mounted power distribution bar and (ii) a corresponding second bond wire that connects the power distribution bar to a corresponding bond pad on the IC die. As such, different types of packaged IC devices having different numbers and/or configurations of power distribution bars can be assembled using a single, generic lead frame design having a die pad, tie bars, and leads, but no power distribution bars.

Abstract: A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.

Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.

Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.

Abstract: A lead frame includes a lead formed of a conductive material and having first and second ends, opposing first and second main surfaces, and opposing first and second side surfaces each extending between the first and second main surfaces. A polymeric layer is formed at least on the first main surface and the first and second side surfaces of the lead at least proximate the second end of the lead. An opening in the polymeric layer on the first main surface of the lead proximate the second end is provided for connecting the lead to, for example, a semiconductor die via a bond wire.

Abstract: A packaged semiconductor device has a lead frame, a semiconductor die, and bond wires. The lead frame has a two-dimensional array of leads with a subset of interior leads located in the interior of the array that do not extend to the perimeter of the array. The bond wires are connected to the semiconductor die and respective ones of the leads of the array.

Abstract: A lead frame includes a lead formed of a conductive material and having first and second ends, opposing first and second main surfaces, and opposing first and second side surfaces each extending between the first and second main surfaces. A polymeric layer is formed at least on the first main surface and the first and second side surfaces of the lead at least proximate the second end of the lead. An opening in the polymeric layer on the first main surface of the lead proximate the second end is provided for connecting the lead to, for example, a semiconductor die via a bond wire.

Abstract: A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process.

Abstract: A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.

Abstract: A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process.

Abstract: A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.

Abstract: A surface mount semiconductor device has a semiconductor die encapsulated in a molding compound. Electrical contact elements of an intermediate set are disposed on the molding compound. A set of coated wires electrically connect bonding pads of the semiconductor die and the electrical contact elements of the intermediate set. A layer of insulating material covers the coated wires, the die and the electrical contact elements of the intermediate set. Electrically conductive elements are exposed at an external surface of the layer of insulating material and contact respective electrical contact elements of the intermediate set through the layer of insulating material.

Abstract: A surface mount semiconductor device has a semiconductor die encapsulated in a molding compound. Electrical contact elements of an intermediate set are disposed on the molding compound. A set of coated wires electrically connect bonding pads of the semiconductor die and the electrical contact elements of the intermediate set. A layer of insulating material covers the coated wires, the die and the electrical contact elements of the intermediate set. Electrically conductive elements are exposed at an external surface of the layer of insulating material and contact respective electrical contact elements of the intermediate set through the layer of insulating material.