Abstract: The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.

Abstract: A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: The invention includes methods of forming deuterated silicon nitride-containing materials from at least one deuterated nitrogen compound in combination with one or more silicon-containing compounds that do not contain hydrogen isotopes. Suitable deuterated nitrogen compounds can comprise, for example, NH2D, NHD2 and ND3. Suitable silicon-containing compounds include, for example, SiCl4 and Si2Cl6. Deuterated silicon nitride-containing materials of the present invention can be incorporated into, for example, transistor devices. The transistor devices can be utilized in DRAM cells, which in turn can be utilized in electronic systems.

Abstract: A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

Abstract: A process of forming a capacitor structure over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

Abstract: A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

Abstract: A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

Abstract: This invention pertains to a method for the systematic development of integrated chip technology. The method may include obtaining empirical data of parameters for an existing integrated circuit manufacturing process and extrapolating the known data to a new technology to assess potential yields of the new technology from the known process. Further, process variables of the new process may be adjusted based upon the empirical data in order to optimize the yields of the new technology. A logic based computing system such as a fuzzy logic or neural-network system may be utilized. The computing system may also be utilized to improve the yields of an existing manufacturing process by adjust process variables within downstream process tools based upon data collected in upstream process for a particular semiconductor substrate or lot.

Abstract: Disclosed is a method of selective oxidation of components of a semiconductor transistor containing silicon in the presence of high conductivity metal or metal alloys. A high temperature annealing step allows hydrogen gas to permeate the surface of a metal or metal alloy and creates a hydrogen-terminated passivation layer that surrounds the metallic layer. This passivating layer protects the underlying metal or metal alloy from oxidation by oxygen or water and reduces any oxidized metal present back into the constituent metal or metal alloy. In a subsequent wet oxidation step the source and drain regions of a semiconductor transistor gate electrode are reoxidized without oxidation of the passivated metal or metal alloy. The process does not consume the metal or metal alloy layer, insures that the overall gate electrode resistance remains low, and preserves the desirable characteristics of the gate electrode that insure a quality component with superior longevity.

Abstract: This invention pertains to a method for the systematic development of integrated chip technology. The method may include obtaining empirical data of parameters for an existing integrated circuit manufacturing process and extrapolating the known data to a new technology to assess potential yields of the new technology from the known process. Further, process variables of the new process may be adjusted based upon the empirical data in order to optimize the yields of the new technology. A logic based computing system such as a fuzzy logic or neural-network system may be utilized. The computing system may also be utilized to improve the yields of an existing manufacturing process by adjust process variables within downstream process tools based upon data collected in upstream process for a particular semiconductor substrate or lot.

Abstract: This invention pertains to a method for the systematic development of integrated chip technology. The method may include obtaining empirical data of parameters for an existing integrated circuit manufacturing process and extrapolating the known data to a new technology to assess potential yields of the new technology from the known process. Further, process variables of the new process may be adjusted based upon the empirical data in order to optimize the yields of the new technology. A logic based computing system such as a fuzzy logic or neural-network system may be utilized. The computing system may also be utilized to improve the yields of an existing manufacturing process by adjust process variables within downstream process tools based upon data collected in upstream process for a particular semiconductor substrate or lot.