Patents by Inventor Lyle Edwin Grosbach
Lyle Edwin Grosbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7660251Abstract: A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.Type: GrantFiled: March 9, 2008Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Lyle Edwin Grosbach, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Patent number: 7567137Abstract: A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring oscillator counts a number of clocks and determines when to switch the reference clock. For example, a clock edge time is recorded as a two-byte field, where a high byte records a programmable number of fast clocks per clock edge, and a low byte records a fraction of a clock edge. Each time the reference clock switches a count down counter is loaded with the high byte, and the low byte is added to the current fraction. If the fraction has a carry, an additional fast clock is added to the count down counter.Type: GrantFiled: December 7, 2007Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Lyle Edwin Grosbach, Quentin Gustave Schmierer
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Publication number: 20080159297Abstract: A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.Type: ApplicationFiled: March 9, 2008Publication date: July 3, 2008Applicant: International Business Machines CorporationInventors: Lyle Edwin Grosbach, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Patent number: 7362706Abstract: A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.Type: GrantFiled: December 12, 2002Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Lyle Edwin Grosbach, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Patent number: 7319367Abstract: A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring oscillator counts a number of clocks and determines when to switch the reference clock. For example, a clock edge time is recorded as a two-byte field, where a high byte records a programmable number of fast clocks per clock edge, and a low byte records a fraction of a clock edge. Each time the reference clock switches a count down counter is loaded with the high byte, and the low byte is added to the current fraction. If the fraction has a carry, an additional fast clock is added to the count down counter.Type: GrantFiled: February 1, 2006Date of Patent: January 15, 2008Assignee: International Business Machines CorporationInventors: Lyle Edwin Grosbach, Quentin Gustave Schmierer
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Publication number: 20040114517Abstract: A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.Type: ApplicationFiled: December 12, 2002Publication date: June 17, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lyle Edwin Grosbach, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Patent number: 6523080Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.Type: GrantFiled: January 27, 1998Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Lyle Edwin Grosbach, Kent Harold Haselhorst, David John Krolak, James Anthony Marcella, Peder James Paulson
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Patent number: 5751990Abstract: A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by pointers to entries in the translation lookaside buffer. This eliminates redundant listings of the virtual and real addresses for the cache line from the cache directory allowing the directory to be small in size. Upon a memory access by a processing unit, a cache hash address is generated to access a translation lookaside buffer entry allowing comparison of the address stored in the TLB entry with the address of the memory access. Congruence implies a hit. Concurrently, the cache hash address indicates a pointer from the cache directory. The pointer should correspond to the cache hash address to indicate a cache directory hit. Where both occur a cache hit has occurred.Type: GrantFiled: April 26, 1994Date of Patent: May 12, 1998Assignee: International Business Machines CorporationInventors: David John Krolak, Lyle Edwin Grosbach, Sheldon B. Levenstein, John David Irish
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Patent number: 5748919Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.Type: GrantFiled: July 10, 1996Date of Patent: May 5, 1998Assignee: International Business Machines CorporationInventors: Herman Lee Blackmon, Robert Allen Drehmel, Lyle Edwin Grosbach, Kent Harold Haselhorst, David John Krolak, James Anthony Marcella, Peder James Paulson
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Patent number: 5649177Abstract: The ability to harmonize the activities of individual computer system components with control signals is key to the operation of any computer system. Examples of this need for control include the need to write data to multiple registers on the same clock cycle, the need to clear values on multiple entities on the same clock cycle, and the need to stop and start the master clock pulse train itself. In the past, providing this control was not a problem because control signals could be reliably sent to all the timing dependent components within a single cycle of the master clock pulse train. This control methodology is called "single cycle control." Today, however, single cycle control is not trustworthy in all situations. Master clock pulse trains are so fast that single cycle control is no longer reliable when timing dependent components reside in locations distant from the control signal generating circuitry.Type: GrantFiled: November 28, 1995Date of Patent: July 15, 1997Assignee: International Business Machines CorporationInventors: Lyle Edwin Grosbach, David John Krolak, David Wayne Marquart