Abstract: A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring oscillator counts a number of clocks and determines when to switch the reference clock. For example, a clock edge time is recorded as a two-byte field, where a high byte records a programmable number of fast clocks per clock edge, and a low byte records a fraction of a clock edge. Each time the reference clock switches a count down counter is loaded with the high byte, and the low byte is added to the current fraction. If the fraction has a carry, an additional fast clock is added to the count down counter.

Abstract: A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring oscillator counts a number of clocks and determines when to switch the reference clock. For example, a clock edge time is recorded as a two-byte field, where a high byte records a programmable number of fast clocks per clock edge, and a low byte records a fraction of a clock edge. Each time the reference clock switches a count down counter is loaded with the high byte, and the low byte is added to the current fraction. If the fraction has a carry, an additional fast clock is added to the count down counter.

Abstract: In a first aspect, a method of testing or analyzing an integrated circuit (IC) is provided. The method includes the steps of (1) generating information about a dependency between components of the IC based on a netlist describing the IC; and (2) reducing the generated information by at least one of (a) combining portions of the information about components with a common dependency; and (b) eliminating a portion of the information about at least a first component that does not depend on another component of the IC. Numerous other aspects are provided.

Abstract: In a first aspect of the invention, a first method is provided for hierarchical scheduling. The first method includes the steps of (1) selecting a first winning entry from one of a plurality of main calendars during a time unit, the first winning entry indicating a first pipe to be serviced during the time unit (2) determining that no pipe flow corresponding to the winning first pipe currently needs to be serviced during the time unit (3) selecting a second winning entry from the plurality of main calendars during the time unit, the second winning entry indicating a second pipe or an autonomous flow to be serviced during the time unit; and (4) servicing the autonomous flow or a pipe flow corresponding to the second winning entry during the time unit. Numerous other aspects are provided.

Abstract: In a first aspect, a method is provided for scheduling connections for a network processor. The method includes the steps of, in a cache, scheduling a plurality of connections to be serviced based on quality of service parameters stored in a control structure corresponding to each connection and during a scheduling opportunity (1) identifying one or more of the plurality of connections in the cache to be serviced; (2) selecting one of the connections identified to be serviced; (3) servicing the selected connection; (4) accessing one or more portions of the control structure in the cache; (5) calculating a next service time when the selected connection is to be serviced; and (6) determining whether to schedule the selected connection to be serviced in one of the cache and a calendar based on the next service time. Numerous other aspects are provided.