Patents by Inventor Lyle K. Mantz, II

Lyle K. Mantz, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip identification using top metal layer
    Patent number: 8242603
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Joseph J. Check, Edward B. Harris, Lyle K. Mantz, II, Richard R. Kiser, Patricia J. Leith
  • CHIP IDENTIFICATION USING TOP METAL LAYER
    Publication number: 20100270684
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.
    Type: Application
    Filed: December 10, 2007
    Publication date: October 28, 2010
    Applicant: AGERE SYSTEMS INC.
    Inventors: Joseph J. Check, Edward B. Harris, Lyle K. Mantz, II, Richard R. Kiser, Patricia J. Leith