Patents by Inventor Lyle Peterson

Lyle Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991348
    Abstract: An illustrated view of an exemplary guitar pick for strumming guitar strings is presented. The guitar pick is useful for always being in a proper place for strumming the guitar strings. The guitar pick is further easy to place on one's finger and to use. The guitar pick is further efficient in costs.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 27, 2021
    Inventor: Lyle Peterson
  • Patent number: 10469979
    Abstract: A method for managing data access in a mobile device is provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patrick Joseph Bohrer, Ahmed Gheith, James Lyle Peterson
  • Patent number: 8990831
    Abstract: A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8510749
    Abstract: A system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 8417913
    Abstract: A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, James Lyle Peterson, Ramakrishnan Rajamony, Hazim Shafi
  • Publication number: 20120317228
    Abstract: A method for managing data access in a mobile device is provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.
    Type: Application
    Filed: April 30, 2012
    Publication date: December 13, 2012
    Applicant: International Business Machines Corporation
    Inventors: PATRICK JOSEPH BOHRER, AHMED GHEITH, JAMES LYLE PETERSON
  • Publication number: 20120317234
    Abstract: A, system, and computer program product for managing data access in a mobile device are provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph BOHRER, Ahmed GHEITH, James Lyle PETERSON
  • Publication number: 20120227048
    Abstract: A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 6, 2012
    Applicant: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Publication number: 20110296423
    Abstract: A method, system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: ELMOOTAZBELLAH NABIL ELNOZAHY, Heather Lynn Hanson, James Lyle Peterson, Freeman Leigh Rawson, III, Malcolm Scott Ware
  • Patent number: 7231509
    Abstract: An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible only to extended register instructions. The processor maps extended register references to physical extended registers at run time. The processor includes a configurable extended register mapping unit to support this functionality. The mapping unit is accessible to an instruction decoder, which detects extended register references and forwards them to the mapping unit. The mapping unit returns a physical extended register corresponding to the extended register reference in the instruction. The mapping unit is configurable so that, for example, the mapping is specific to a code block. An extended register allocation instruction causes the processor to allocate a portion of the extended register set to the code block in which the declaration is located and to configure the mapping unit to reflect the allocation.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: June 12, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Gheith, James Lyle Peterson, Richard Ormond Simpson
  • Patent number: 7080214
    Abstract: A multiprocessor system includes a plurality of data processing nodes. Each node has a processor coupled to a system memory, a cache memory, and a cache directory. The cache directory contains cache coherency information for a predetermined range of system memory addresses. An interconnection enables the nodes to exchange messages. A node initiating a function shipping request identifies an intermediate destination directory based on a list of the function's operands and sends a message indicating the function and its corresponding operands to the identified destination directory. The destination cache directory determines a target node based, at least in part, on its cache coherency status information to reduce memory access latency by selecting a target node where all or some of the operands are valid in the local cache memory. The destination directory then ships the function to the target node over the interconnection.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: James Lyle Peterson, Ramakrishnan Rajamony, Hazim Shafi
  • Patent number: 7020700
    Abstract: An Internet client is provided with a SOCKS server. The client comprises a processor having an operating system, and a suite of one or more Internet tools. The SOCKS proxy server includes means for intercepting and servicing connection requests from the Internet tools. Preferably, the proxy server has a predetermined Internet Protocol address, preferably the loopback address. If the loopback address is not available on the protocol stack, a redirecting mechanism is used to redirect connection requests associated with stale IP addresses to a current IP address. The SOCKS server includes a filtering mechanism for filtering connection requests to particular servers, and a monitoring mechanism for monitoring network IP activity.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: March 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Craig Alan Bennett, Christian Lita, James Lyle Peterson, Joseph Raymond Thompson
  • Patent number: 6934115
    Abstract: A timing based servo alignment system that uses a set of band identification marks to determine which data band is being currently read. The system uses a read module having a plurality of band identification read elements. The band identification read elements are placed on the read module such that each band identification read element is aligned only to the band identification marks when a corresponding data band is aligned to the data read element.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: August 23, 2005
    Assignee: Storage Technology Corporation
    Inventors: Steven Michael Kientz, David Lyle Peterson
  • Patent number: 6708181
    Abstract: A method for initializing variables within class objects in a statically loaded object-oriented programming language. A two-phase flooding algorithm is utilized to initialize the core variables within each class along with those variables needed to be initialized before the core variables. An initialization algorithm is performed within each of the class objects in a recursive manner. Once a class object has begun the initialization process internally, calls to again begin the initialization process within that class object from another class object will result in a return in order to prevent duplicates of the initialization process from being performed within each of the class objects.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventor: James Lyle Peterson
  • Publication number: 20040015684
    Abstract: In one form of the invention, a method for scheduling multiple instruction threads for a processor in an information handling system includes communicating, to processor circuitry by an operating system, a selected schedule of instruction threads for a set of instructions. The processor circuitry switches from executing one of the threads with one of the contexts to executing another of the threads with another of the contexts, responsive to the schedule received from the operating system.
    Type: Application
    Filed: May 30, 2002
    Publication date: January 22, 2004
    Applicant: International Business Machines Corporation
    Inventor: James Lyle Peterson
  • Patent number: 6490670
    Abstract: A method and apparatus for managing memory allocation. Each memory block category contains memory blocks. A request, including an object size, is received to allocate memory to an object. An available memory block is allocated to the object if the memory block category for size corresponding to the object size of the object contains an available memory block. An available memory block from a memory block category having a memory block size larger than the object size is located if an available memory block is absent in the memory block category for sizes corresponding to the object size. The located available memory block is partitioned into memory blocks, having a size corresponding to the object size. A partitioned memory block from the partitioned memory blocks is allocated to the object.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: December 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Collins, James Lyle Peterson, Weining Gu
  • Patent number: 6421775
    Abstract: A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: July 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, David Brian Glasco, James Lyle Peterson, Ramakrishnan Rajamony, Ronald Lynn Rockhold
  • Patent number: 5668943
    Abstract: A system and method for recovering from failures in the disk access path of a clustered computing system. Each node of the clustered computing system is provided with proxy software for handling physical disk access requests from applications executing on the node and for directing the disk access requests to an appropriate server to which the disk is physically attached. The proxy software on each node maintains state information for all pending requests originating from that node. In response to detection of a failure along the disk access path, the proxy software on all of the nodes directs all further requests for disk access to a secondary node physically attached to the same disk.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: September 16, 1997
    Assignee: International Business Machines Corporation
    Inventors: Clement Richard Attanasio, Maria Angela Butrico, James Lyle Peterson, Christos Alkiviadis Polyzois, Stephen Edwin Smith
  • Patent number: 4650469
    Abstract: A system for delivering a drug to a patient according to the preferred embodiment of the present invention is shown as being of modular construction including a control module and a reservoir module. The reservoir module is removably secured to the control module by a removable hinge member at one end and a locking member at the other end. The reservoir module includes a pressure plate upon which a tube extending from a drug container bag to the patient is supported. The control module includes a pumping mechanism including a camshaft which reciprocates valves and an expulsor in the control module engaging and interacting with the tube located on the pressure plate for forcing the drug from the drug container bag to the patient. In its most preferred form, the pressure plate includes standoffs which abut with the pump chassis for insuring proper spacing maintenance between the pressure plate of the reservoir module and the control module.
    Type: Grant
    Filed: August 27, 1985
    Date of Patent: March 17, 1987
    Assignee: Deltec Systems, Inc.
    Inventors: Harvey F. Berg, Lyle Peterson, James E. Leslie, Phong Doan
  • Patent number: 4559038
    Abstract: A system for delivering a drug to a patient according to the preferred embodiment of the present invention is shown as being of modular construction including a control module and a reservoir module. The reservoir module is removably secured to the control module by a removable hinge member at one end and a locking member at the other end. The reservoir module includes a pressure plate upon which a tube extending from a drug container bag to the patient is supported. The control module includes a pumping mechanism including a camshaft which reciprocates valves and an expulsor in the control module. The valves and expulsor engage and interact with the tube located on the pressure plate for forcing the drug from the drug container bag to the patient. In its most preferred form, the pressure plate includes standoffs which abut with the pump chassis for insuring proper spacing maintenance between the pressure plate of the reservoir module and the control module.
    Type: Grant
    Filed: October 19, 1984
    Date of Patent: December 17, 1985
    Assignee: Deltec Systems, Inc.
    Inventors: Harvey F. Berg, Lyle Peterson, James E. Leslie