Patents by Inventor Lyle Smith

Lyle Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8122413
    Abstract: Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.
    Type: Grant
    Filed: June 9, 2007
    Date of Patent: February 21, 2012
    Assignee: Otrsotech, Limited Liability Company
    Inventors: Pat Hom, Steven Eplett, Rabi Sengupta, Eric West, Lyle Smith
  • Publication number: 20100169856
    Abstract: Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.
    Type: Application
    Filed: June 9, 2007
    Publication date: July 1, 2010
    Inventors: Pat Hom, Steven Eplett, Rabi Sengupta, Eric West, Lyle Smith
  • Publication number: 20090126089
    Abstract: A toilet ventilation system that includes a ventilation collar mountable between a toilet tank and a toilet base. The ventilation collar cooperates with the toilet base for removal of odoriferous air from the toilet bowl via ports in the toilet rim through the ventilation collar. A fan extracts the air from the ventilation collar. A baffle disposed within the ventilation collar prevents water from being extracted from the vent collar.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 21, 2009
    Inventor: Lyle Smith
  • Publication number: 20070011853
    Abstract: This invention provides a system and method for attaching a trim cover to a flexible/resilient substrate, typically constructed from foam, which includes a plurality of clips that each has a base molded into the substrate. The bases each include a central “keyhole” slot that receives a corresponding key formed on a stem at a bottom of a clip projection. The clip projection defines a cavity for receiving a trim cover bead through a gap formed between a pair of legs that extend from the bottom. The stem has a length that is approximately the thickness of the slot. By passing the key through the slot and rotating the key to a locked position, the clip projection may be removably mounted to the substrate for repair or replacement as needed. The base may be constructed from a material that adheres effectively to the substrate, while the clip projection may be constructed from a material that exhibits high elasticity and wear-resistance.
    Type: Application
    Filed: July 13, 2005
    Publication date: January 18, 2007
    Inventor: Lyle Smith
  • Patent number: 7043713
    Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 9, 2006
    Assignee: Lightspeed Semiconductor Corp.
    Inventors: Robert Osann, Jr., Shafy Eltoukhy, Shridhar Mukund, Lyle Smith
  • Patent number: 7037102
    Abstract: A plunger machine for molding reinforced polymer compositions is provided. The plunger machine has particular application in molding polymer that is reinforced with particles having an aspect ratio that is greater than 1:1. The plunger machine includes a barrel housing with a smooth walled barrel with longitudinal fins projecting inwardly towards the center of the bore that defines a main melt chamber. A plunger housing, having a plunger bore, defines an initial melt chamber and is in communication with the main melt chamber. A plunger resides in the plunger bore and is reciprocatable therein. The barrel bore is continuously inwardly tapered and cooperates with the longitudinal fins to provide a shortened melt period and a smooth transition and alignment of reinforcing members within the polymer mixture during the melt process.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: May 2, 2006
    Assignee: Cool Options, Inc.
    Inventor: Lyle Smith
  • Patent number: 6885043
    Abstract: An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: April 26, 2005
    Assignee: Lightspeed Semiconductor Corporation
    Inventors: Lyle Smith, Eric Dellinger, Eric West, Shridhar Mukund
  • Patent number: 6769109
    Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: July 27, 2004
    Assignee: Lightspeed Semiconductor Corporation
    Inventors: Robert Osann, Jr., Shafy Eltoukhy, Shridhar Mukund, Lyle Smith
  • Publication number: 20040049759
    Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.
    Type: Application
    Filed: August 12, 2003
    Publication date: March 11, 2004
    Inventors: Robert Osann, Shafy Eltoukhy, Shridhar Mukund, Lyle Smith
  • Patent number: 6696856
    Abstract: Described herein is an ASIC having an array of predesigned function blocks. The function blocks can be used to implement combinational logic, sequential logic, or a combination of both. The function blocks also have a selectable output drive strength. The output drive strength can be selected, in some embodiments, using mask programming.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: February 24, 2004
    Assignee: Lightspeed Semiconductor Corporation
    Inventors: Lyle Smith, Eric Dellinger, Eric West, Shridhar Mukund
  • Patent number: 6694491
    Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: February 17, 2004
    Assignee: Lightspeed Semiconductor Corporation
    Inventors: Robert Osann, Jr., Shafy Eltoukhy, Shridhar Mukund, Lyle Smith
  • Publication number: 20030155587
    Abstract: An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors.
    Type: Application
    Filed: January 18, 2002
    Publication date: August 21, 2003
    Inventors: Lyle Smith, Eric Dellinger, Eric West, Shridhar Mukund
  • Publication number: 20020010903
    Abstract: In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.
    Type: Application
    Filed: June 8, 2001
    Publication date: January 24, 2002
    Inventors: Robert Osann, Shafy Eltoukhy, Shridhar Mukund, Lyle Smith
  • Patent number: 4573900
    Abstract: An apparatus is disclosed for controlling operating pressure within a mold cavity of an injection molding die. Finely detailed, and parts having thin walls are molded with the invention providing a process for eliminating defects. There is a pressure control apparatus which is preset to provide varying degrees of negative and positive pressure during the mold cycle, and to reset to repeat the procedure for subsequent cycles. The procedure includes a cleaning stage for preparing the mold cavity for the following mold cycle.
    Type: Grant
    Filed: December 6, 1984
    Date of Patent: March 4, 1986
    Assignee: Alpha Molding Technologies Associates
    Inventor: Lyle Smith