Abstract: A memory device incorporates a serial data bus coupled to a serial bus control circuit to provide access to error correction event notification information and error correction function configuration information. In some embodiments, the serial bus control circuit is in communication with a set of registers storing error correction event information and error correction function configuration information. The serial data bus enables access to the error correction control functions and to the error correction event notification information without interfering with and independent of the normal memory operation of the memory device.

Abstract: A memory device incorporates a serial data bus coupled to the control circuit of the memory device to provide direct access to the error correction control circuit and to the error correction event notification information and error correction function configuration information stored in mode registers of the control circuit. The serial data bus enables access to the error correction control functions and to the error correction event notification information without requiring modifications to the memory controller used to control and communicate with the memory device.

Abstract: A memory device incorporates a serial data bus coupled to a serial bus control circuit to provide access to error correction event notification information and error correction function configuration information. In some embodiments, the serial bus control circuit is in communication with a set of registers storing error correction event information and error correction function configuration information. The serial data bus enables access to the error correction control functions and to the error correction event notification information without interfering with and independent of the normal memory operation of the memory device.

Abstract: A memory device incorporates a serial data bus coupled to the control circuit of the memory device to provide direct access to the error correction control circuit and to the error correction event notification information and error correction function configuration information stored in mode registers of the control circuit. The serial data bus enables access to the error correction control functions and to the error correction event notification information without requiring modifications to the memory controller used to control and communicate with the memory device.

Abstract: A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.

Abstract: A method in a memory device implementing error correction includes setting an error correction event register to a first value; assessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the assessed memory location in the first memory array and retrieving error correction check bits corresponding to the assessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.

Abstract: A memory device includes one or more memory semiconductor chips housed in a surface-mount semiconductor package and formed on a package substrate. The package substrate includes a two-dimensional array of package leads for connecting signals of the one or more memory semiconductor chips to an external system. The memory assembly has a package pin-out being a mirror image of a memory interface pin-out of a processor. In other embodiments, a circuit module includes a printed circuit board, a processor mounted on a first side of the printed circuit board and a memory assembly mounted on a second, opposite side of the printed circuit board. The memory assembly has a memory assembly pin-out that is a mirror image of the memory interface pin-out of the processor and the memory assembly is positioned in direct alignment with the memory interface pin-out of the processor.

Abstract: A digital circuit is used to demodulate a linear chirp spread spectrum signal. The digital circuit uses a counter which is clocked so as to count during the time period between the pulses of a chirp signal. The circuitry also uses a digital filter to determine whether the frequencies of the linear chirp signal are within the correct bandwidth. The output of the counter is compared with the previous count to produce a difference count. A processor uses this difference count value to determine the characteristics of a chirp signal being decoded. A difference signal test circuit provides a digital filter for the difference count to eliminate spurious noise conditions.

Abstract: A central processing unit (CPU) and a dedicated pulse generating and demodulating logic circuit are used to both generate and demodulate a wide variety of pulse signals. Although the CPU exercises general supervision of the dedicated logic circuit, the circuit is arranged to perform most operations independently. Counters, registers and controlling logic generate a pulse stream. This same circuit, with the addition of edge detectors, demodulates (learns) the characteristics of an existing pulse signal in order to be able to generate a replica of that existing signal. An example application of the circuit is with television and other electronic equipment remote control units that include a learning capability.